Dinesh Kumar Jayaraman Rajendiran

Real-time monitoring of blood pressure is crucial for detecting early hypertension and other cardiovascular diseases. However, the common method of measuring blood pressure remains invasive and intermittent, causing inconvenience and discomfort to patients. Smartwatches as a potential platform for continuous blood pressure (BP) measurements have recently attracted a great deal of interest, thanks to developments in wearables, and have been approached with different methodologies. In this paper, we propose a deep learning-based framework for predicting wearable blood pressure using smartwatch sensors. We utilize the smartwatch's optical heart rate sensor and accelerometer to collect physiological signals, including heart rate and motion. A DCNN, followed by an LSTM, is used on the signal values. The concatenated features are then fed to the regression model for estimating blood pressure from the concatenated features using a CNN-LSTM. A dataset of 50 participants' physiological signals and ground-truth blood pressures is collected to validate and test the framework. Datasets: The dataset was partitioned into training, validation, and test splits, which were used to train and test our framework. Our method achieved mean errors of 3.26 mmHg for systolic blood pressure (SBP) and 2.12 mmHg for diastolic blood pressure (DBP), which were superior to state-of-the-art results. This work enables smartwatches for non-intrusive and effortless blood pressure monitoring processes with long-term and online applications. It can be worn daily, and we use the Teal-Time blood pressure tracker to identify certain abnormal blood flow patterns. This could significantly impact the control of these conditions (such as hypertension) and likely improve overall health. For these factors, our system is generalizable to other wearables, allowing it to be widely used in the population. Our study demonstrated that blood pressure (BP) was monitored continuously under a real-world setting using a smartwatch and played a significant role in healthcare.

The Internet of Medical Things (IoMT) is one of the growing and emerging technologies in recent trends. Faster computation is the major requirement of any edge computing device. Edge computing systems require Effective Computation Blocks (ECB) to store and process signals between users and the cloud. The time taken for trans-receiving and processing of the signal should be minimal, which is mentioned as latency. The ECB assures high-end power transmissions, especially in autonomous vehicles, robotic surgery, diagnosis, and medicine distributions. The ECB architecture is based on highly effective computation. The computation is independent of internet connectivity and therefore the major suspect is uncertainty. This work focuses on the development of sustainable approximation adder for edge devices of IoMT. This architecture performance is measured at the deep learning architectures which are familiar at the edge devices of cloud computing. In cases of low internet, the computing devices are slower, which causes all devices and applications to go down the track. By implementing the proposed adder (PAXA) at the edge, computing gets around the dependencies by locating data that is closer to the possibility, which speeds up applications and improves their availability and also in the applications where it requires high speed and low-power availability.

The Electrocardiogram (ECG) records are crucial for predicting heart diseases and evaluating patient’s health conditions. ECG signals provide essential peak values that reflect reliable health information. Analyzing ECG signals is a fundamental technique for computerized prediction with advancements in Very Large-Scale Integration (VLSI) technology and significantly impacts in biomedical signal processing. VLSI advancements focus on high-speed circuit functionality while minimizing power consumption and area occupancy. In ECG signal denoising, digital filters like Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) are commonly used. The FIR filters are preferred for their higher-order performance and stability over IIR filters, especially in real-time applications. The Modified FIR (MFIR) blocks were reconstructed using the optimized adder-multiplier block for better noise reduction performance. The MIT-BIT database is used as reference where the noises are filtered by the MFIR based on Optimized Kogge Stone Adder (OKSA). Features are extracted and analyzed using Discrete wavelet transform (DWT) and Cross Correlation (CC). At this modern era, Hybrid methods of Machine Learning (HMLM) methods are preferred because of their combined performance which is better than non-fused methods. The accuracy of the Hybrid Neural Network (HNN) model reached 92.3%, surpassing other models such as Generalized Sequential Neural Networks (GSNN), Artificial Neural Networks (ANN), Support Vector Machine with linear kernel (SVM linear), and Support Vector Machine with Radial Basis Function kernel (SVM RBF) by margins of 3.3%, 5.3%, 23.3%, and 24.3%, respectively. While the precision of the HNN is 91.1%, it was slightly lower than GSNN and ANN but higher than both SVM linear and SVM -RBF. The HNN with various features are incorporated to improve the ECG classification. The accuracy of the HNN is switched to 95.99% when the DWT and CC are combined. Also, it improvises other parameters such as precision 93.88%, recall is 0.94, F1 score is 0.88, Kappa is 0.89, kurtosis is 1.54, skewness is 1.52 and error rate 0.076. These parameters are higher than recently developed models whose algorithms and methods accuracy is more than 90%.

Achieving high speed and lesser power in large operand adders is greatly necessitated for incorporating modern portable systems, which are highly demanded in the artificial intelligence sector, especially in deep learning-based applications. Conventional speedy adder structures are based on parallel-prefix (PP) types that have huge power consumption. The modified design is deemed the key solution for contemporary demands in today's modern consumer electronics. The existing hybrid adder (HA) architecture functions on the basis of the framework, in which the least significant carriers are produced in large PP adders quicker than the most-significant ones. The base concept of this HA is to customize the binary to Excess-1 Converter (BEC) and make C_in = 1 in the standard Carry Select Adder (CSA) to reduce power and area than RCA. The key improvement in BEC is minimizing the logic gate counts that are necessitated than FA of n-bit architecture. In the existing KS-RCA, the customized BEC is introduced for achieving considerable performance metrics improvement. All existing work and the proposed adder implementation are done in Cadence tool RTL compiler with 90 nm TSMC technologies using the dynamic power verification and analysis methods of RTL. The proposed technique efficiently diminishes the delay that is 76.39% lesser than the CSEL-BEC , 70.86% lesser than CSEL-RCA, and significantly 3.27% lower than the KS-RCA. Also, power consumption is reduced up to 28.92%, 10.61%, and 11.06% than the existing methods, such as KS-RCA, CSEL-RCA, and CSEL-BEC, respectively. However, the area is efficiently reduced by the proposed method up to 29.52% concerning the maximum value of implemented techniques.

In VLSI design power dissipation is an important factor in micro and nano VLSI design. For Space applications, Circuits with Ultralow power (ULP) operation is a good solution because of its limited options of energy sources. This Ultralow power operation will pay the way to small and low-cost satellites where the heavy battery and power supplies can be replaced. One of the effective way to implement ULP operations are by restricting the VDD and make the circuit to work in sub threshold region. But at the same time this low voltage circuits have some challenges like delay, temperature fluctuations needs to be addressed. The most complicated area of these circuits are memory arrays which cover large areas of the silicon die which often store critical data. Large bit cells leads to hardening of embedded memory block cells and this limits the low power operation of the entire system. In this paper, radiation-hardened static random access memory (SRAM) bit cell targeted at low-voltage functionality is proposed. The proposed method employs 5T RAM cell bears changes in charge deposits as high as 500 fC at a scaled 500-mV supply voltage.