Wujun Xie

This article presents a two-stage interpolation time-to-digital converter (TDC), combining a Vernier gray code oscillator TDC (VGCO-TDC) and a tapped-delay line TDC (TDL-TDC). The proposed TDC uses the Nutt method to achieve a broad, high-resolution measurement range. It utilizes look-up tables based gray code oscillators to build a VGCO-TDC as the first-stage interpolation for fine-time measurements. Then the overtaking residual from the VGCO-TDC is measured by a TDL-TDC to achieve the second-stage interpolation. Due to the two-stage interpolation architecture, the carry-chain-based delay line only needs to cover the resolution of the VGCO-TDC. Hence, we can reduce the delay-line length and related hardware resource utilization. We implemented and evaluated a 16-channel TDC system in Xilinx 20-nm Kintex-UltraScale and 28-nm Virtex-7 field-programmable gate arrays. The Kintex-UltraScale version achieves an average resolution [least significant bit (LSB)] of 4.57 picoseconds (ps) with 4.36 LSB average peak-to-peak differential nonlinearity (DNL _pk-pk ). The Virtex-7 version achieves an average resolution of 10.05 ps with 2.85 LSB average DNL _pk-pk .

This article presents a low-hardware consumption, resolution-configurable, automatically calibrating gray code oscillator time-to-digital converter (TDC) in Xilinx 16-nm UltraScale+, 20-nm UltraScale and 28-nm Virtex-7 field-programmable gate arrays (FPGAs). The proposed TDC utilizes look-up tables as delay elements and has several innovations: 1) a sampling matrix structure to improve the resolution, 2) a virtual bin calibration method (VBCM) to achieve configurable resolutions and automatic calibration, and 3) hardware implementation of the VBCM in standard FPGA devices. We implemented and evaluated a 16-channel TDC system in all three FPGAs. The UltraScale+ version achieved the best resolution (least significant bit, LSB) of 20.97 ps with 0.09 LSB averaged peak-to-peak differential nonlinearity (DNL _pk–pk ). The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps with 0.10 LSB averaged DNL _pk–pk and 34.84 ps with 0.08 LSB averaged DNL _pk–pk , respectively.

We present a fast and accurate analytical method for fluorescence lifetime imaging microscopy (FLIM), using the extreme learning machine (ELM). We used extensive metrics to evaluate ELM and existing algorithms. First, we compared these algorithms using synthetic datasets. The results indicate that ELM can obtain higher fidelity, even in low-photon conditions. Afterwards, we used ELM to retrieve lifetime components from human prostate cancer cells loaded with gold nanosensors, showing that ELM also outperforms the iterative fitting and non-fitting algorithms. By comparing ELM with a computational efficient neural network, ELM achieves comparable accuracy with less training and inference time. As there is no back-propagation process for ELM during the training phase, the training speed is much higher than existing neural network approaches. The proposed strategy is promising for edge computing with online training.

We present a deep learning approach to obtain high-resolution (HR) fluorescence lifetime images from low-resolution (LR) images acquired from fluorescence lifetime imaging (FLIM) systems. We first proposed a theoretical method for training neural networks to generate massive semi-synthetic FLIM data with various cellular morphologies, a sizeable dynamic lifetime range, and complex decay components. We then developed a degrading model to obtain LR-HR pairs and created a hybrid neural network, the spatial resolution improved FLIM net (SRI-FLIMnet) to simultaneously estimate fluorescence lifetimes and realize the nonlinear transformation from LR to HR images. The evaluative results demonstrate SRI-FLIMnet’s superior performance in reconstructing spatial information from limited pixel resolution. We also verified SRI-FLIMnet using experimental images of bacterial infected mouse raw macrophage cells. Results show that the proposed data generation method and SRI-FLIMnet efficiently achieve superior spatial resolution for FLIM applications. Our study provides a solution for fast obtaining HR FLIM images.

This article proposes a weighted histogram calibration method and an automatic calibration architecture to implement high-linearity time-to-digital converters (TDCs) in low-cost Advanced RSIC Machine (ARM)-based system-on-chips (SoCs). The proposed method significantly reduces the nonlinearity introduced by nonuniform bins. It offers automatic calibration without manual interventions using ARM processors. Besides, our design is cost-effective in hardware consumption. We implemented and evaluated a 16-channel TDC system in a low-cost Zynq-7000 ARM-based SoC, in which the programable logic is equivalent to a 28 nm Artix-7 FPGA. The proposed TDC offers a resolution of 9.83 ps with good uniformity, achieving an averaged ${\rm{DN}}{{\rm{L}}_{{\rm{pk}} - {\rm{pk}}}}$ of 0.38 LSB, and an averaged ${\rm{IN}}{{\rm{L}}_{{\rm{pk}} - {\rm{pk}}}}$ of 0.63 LSB.

Measuring fluorescence lifetimes of fast-moving cells or particles have broad applications in biomedical sciences. This paper presents a dynamic fluorescence lifetime sensing (DFLS) system based on the time-correlated single-photon counting (TCSPC) principle. It integrates a CMOS 192 × 128 single-photon avalanche diode (SPAD) array, offering an enormous photon-counting throughput without pile-up effects. We also proposed a quantized convolutional neural network (QCNN) algorithm and designed a field-programmable gate array embedded processor for fluorescence lifetime determinations. The processor uses a simple architecture, showing unparallel advantages in accuracy, analysis speed, and power consumption. It can resolve fluorescence lifetimes against disturbing noise. We evaluated the DFLS system using fluorescence dyes and fluorophore-tagged microspheres. The system can effectively measure fluorescence lifetimes within a single exposure period of the SPAD sensor, paving the way for portable time-resolved devices and shows potential in various applications.

This article proposes a new calibration method, called the mixed-binning (MB) method, to pursue high-linearity time-to-digital converters (TDCs) for light detection and ranging applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in field-programmable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged ${{\bf DN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$ and ${{\bf IN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$ are close to or even less than 0.05 LSB in multichannel designs.

The wave union (WU) method is a well-known method in time-to-digital converters (TDCs) and can improve TDC performances without consuming extra logic resources. However, an earlier study concluded that the WU method is not suitable for UltraScale field-programmable gate array (FPGA) devices, due to more severe bubble errors. This article proves otherwise and presents new strategies to pursue high-resolution TDCs in Xilinx UltraScale 20 nm FPGAs. Combining our new subtapped delay line (sub-TDL) architecture (effective in removing bubbles and zero-width bins) and the WU method, we found that the wave union method is still powerful in UltraScale devices. We also compared the proposed TDC with the TDCs combining the dual sampling structure and the sub-TDL technique. A binning method is introduced to improve the linearity. Moreover, we derived a formula of the total measurement uncertainties for a single-stage TDL-TDC to obtain its root-mean-square resolution. Compared with the previously published FPGA-TDCs, we presented (for the first time) much more detailed precision analysis for single-TDL TDCs.