Di Yan
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Di Yan has a total of 6 co-authors. Here are the top co-authors by number of shared publications:
- Xiao-Wei Zhang
School of Information Engineering, Xijing University, Xi’an, China
4 shared publications - Lei Zuo
National Key Laboratory of Radar Signal Processing, Xidian University, Xian, China
3 shared publications - Weixing Wang
School of Information Engineering, Chang’an University, Xi’an, China
2 shared publications - Jian-Xin Guo
School of Information Engineering, Xijing University, Xian, China
1 shared publication - Ming Li
National Key Laboratory of Radar Signal Processing, Xidian University, Xian, China
1 shared publication Wei-Xing Wang
School of Information and Communication, Chang’an University, Xi’an, China
1 shared publication
Latest Publications
- 14 November 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Vehicular Technology
- Vol. 72 (5) , 5782-5797
High-Performance of Eigenvalue Decomposition on FPGA for the DOA Estimation
For the direction of arrival (DOA) in array signal processing, eigenvalue decomposition (EVD) is one key issue in hardware implementation of the multiple signal classification (MUSIC) algorithm. Therefore, we introduce the look-ahead sim- plified one-sided Jacobi's method to efficiently decompose those symmetric matrices in this article and prove that the new method has the best orthogonality of eigenvector and locates eigenvectors closest to the true solution in theory. Both the numerical perform- ance and real-time are important in engineering, so we present the novel flexible hardware architecture in single floating point arithmetic for EVD on field-programmable gate arrays (FPGAs). Finally, the simulated and raw data are used to investigate the performance of some different approaches in the context of both the EVD and MUSIC algorithm. The experimental results show that our proposed method has the best performance.
- 14 November 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Vehicular Technology
- Vol. 72 (5) , 5782-5797
High-Performance of Eigenvalue Decomposition on FPGA for the DOA Estimation
For the direction of arrival (DOA) in array signal processing, eigenvalue decomposition (EVD) is one key issue in hardware implementation of the multiple signal classification (MUSIC) algorithm. Therefore, we introduce the look-ahead sim- plified one-sided Jacobi's method to efficiently decompose those symmetric matrices in this article and prove that the new method has the best orthogonality of eigenvector and locates eigenvectors closest to the true solution in theory. Both the numerical perform- ance and real-time are important in engineering, so we present the novel flexible hardware architecture in single floating point arithmetic for EVD on field-programmable gate arrays (FPGAs). Finally, the simulated and raw data are used to investigate the performance of some different approaches in the context of both the EVD and MUSIC algorithm. The experimental results show that our proposed method has the best performance.
- 27 September 2022
- Published by Springer Nature in Circuits, Systems, and Signal Processing
- Vol. 42 (3) , 1573-1592
High-Performance Matrix Eigenvalue Decomposition Using the Parallel Jacobi Algorithm on FPGA
- 27 September 2022
- Published by Springer Nature in Circuits, Systems, and Signal Processing
- Vol. 42 (3) , 1573-1592
High-Performance Matrix Eigenvalue Decomposition Using the Parallel Jacobi Algorithm on FPGA
- 11 February 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 68 (7) , 2665-2669
A Novel Scheme for Real-Time Max/Min-Set-Selection Sorters on FPGA
Partial sorting, selecting M largest/smallest numbers from N inputs, is of interest in many applications. Thus, this brief presents a novel scheme for real-time max/min-set-selection sorters on field-programmable gate arrays (FPGAs). Our scheme has good expansibility but no close relation with the vector length, whose basic idea is reducing the programming complexity through the essence of sorting networks for Bitonic sequences. In addition, two modified forms of our scheme are proposed to solve the high data rate sequence and a multiple of 2 max/min-set-selection problem respectively. Finally, the effectiveness of our scheme is demonstrated on one Xilinx XC7VX690T FPGA by performing comparisons with state-of-the-arts.
- 11 February 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 68 (7) , 2665-2669
A Novel Scheme for Real-Time Max/Min-Set-Selection Sorters on FPGA
Partial sorting, selecting M largest/smallest numbers from N inputs, is of interest in many applications. Thus, this brief presents a novel scheme for real-time max/min-set-selection sorters on field-programmable gate arrays (FPGAs). Our scheme has good expansibility but no close relation with the vector length, whose basic idea is reducing the programming complexity through the essence of sorting networks for Bitonic sequences. In addition, two modified forms of our scheme are proposed to solve the high data rate sequence and a multiple of 2 max/min-set-selection problem respectively. Finally, the effectiveness of our scheme is demonstrated on one Xilinx XC7VX690T FPGA by performing comparisons with state-of-the-arts.
- 28 October 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 68 (6) , 2127-2131
Revisiting the Adjoint Matrix for FPGA Calculating the Triangular Matrix Inversion
Due to the robustness, the matrix inversion methods based on matrix factorization are often adopted in engineering while the triangular matrix inversion is one key part of those methods. This brief reviews the adjoint matrix and presents a novel scheme for field-programmable gate arrays (FPGAs) calculating the triangular matrix inversion. Employing the more characteristics of both the triangular matrix and its inversion, the proposed diagonal-wise algorithm for the triangular matrix inver-sion has the high parallelism and extensibility in the hardware implementation and is suitable for the different matrix triangular factorization (QR, LDL, Cholesky and LU). Meanwhile, the recursive diagonal-wise algorithm is designed for the large scale triangular matrices. Compared with the traditional row-/column-wise methods, our algorithm has a good performance at the low computation load. Finally, the experiments are conducted on one Xilinx Virtex-7 FPGA to illustrate the performances of the four different methods.
- 28 October 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 68 (6) , 2127-2131
Revisiting the Adjoint Matrix for FPGA Calculating the Triangular Matrix Inversion
Due to the robustness, the matrix inversion methods based on matrix factorization are often adopted in engineering while the triangular matrix inversion is one key part of those methods. This brief reviews the adjoint matrix and presents a novel scheme for field-programmable gate arrays (FPGAs) calculating the triangular matrix inversion. Employing the more characteristics of both the triangular matrix and its inversion, the proposed diagonal-wise algorithm for the triangular matrix inver-sion has the high parallelism and extensibility in the hardware implementation and is suitable for the different matrix triangular factorization (QR, LDL, Cholesky and LU). Meanwhile, the recursive diagonal-wise algorithm is designed for the large scale triangular matrices. Compared with the traditional row-/column-wise methods, our algorithm has a good performance at the low computation load. Finally, the experiments are conducted on one Xilinx Virtex-7 FPGA to illustrate the performances of the four different methods.