Yunfeng Hu

A 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC switching energy by 96.41% compared to the conventional scheme. The low complexity and the one-LSB common-mode voltage offset of this scheme benefit from the simultaneous switching of the reference voltages of the capacitors corresponding to the positive array and the negative array throughout the entire reference voltage switching process, and the reference voltage of each capacitor in the scheme does not change more than two voltages. The post-layout result shows that the ADC achieves the 54.96 dB SNDR, the 61.73 dB SFDR, and the 0.67 μw power consumption with the 10-bit mode and the 48.33 dB SNDR, the 54.17 dB SFDR, and the 0.47 μw power consumption with the 9-bit mode in a 180 nm process with a 100 kS/s sampling frequency.

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage V_aq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage V_cm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of V_cm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.

In recent years, due to the rise of the Internet of Things (IoT), various sensors have come to be in great demand for IoT devices. Analog-to-digital converters (ADCs) act as an important part of receivers in sensors. To improve the uptime of IoT devices, a bridged-switch energy-efficient switching scheme for successive approximation register (SAR) ADCs with a low-complexity capacitor drive circuit is proposed. The technique of top-plate sampling and closed-loop charge recycling is used in the proposed switching scheme so that neither the first nor the second comparison consumes switching energy. The third comparison uses bridge switches to connect the subarray to the main array, effectively reducing switching’s energy consumption. Only the least significant bit (LSB) is dependent on the accuracy of V_cm; thus, the last comparison consumes little switching energy. The proposed switching scheme achieves an average switching energy value of 47.5 CV²_ref, which is 96.52% lower than that of the conventional capacitor switching scheme and reduces the area by 75%. The other major circuit modules employed are bootstrapped switches, a fully dynamic comparator, and dynamic SAR logic. The proposed ADC was simulated under the conditions of 180 nm CMOS process and 1 MS/s, resulting in a 9.8-bit effective number of bits (ENOB), a signal-to-noise and distortion ratio (SNDR) of 60.76 dB, a spurious-free dynamic range (SFDR) of 69.85 dB, a power consumption of 14.7 μW, and a figure of merit (FoM) of 16.55 fJ/conv.-step.

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor is presented. Based on the two sub-capacitor arrays architecture and the common-mode technique, the proposed switching scheme achieves 98.45% less switching energy over the conventional architecture with common-mode shift in one LSB. The comparator uses a low power dynamic comparator. The sampling switch adopts a bootstrap circuit with low sampling error. SAR logic is composed of Bit-Slice circuit with low power consumption and few transistors. Simulated in 180 nm CMOS process and 1 MS/s sampling rate, the ADC achieves the 60.06 dB SNDR, the 75.43 dB SFDR and the 10.45 μW power consumption.

This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient switching scheme achieves an average digital-to-analog converter switching energy of 63.56 CV_ref², achieving a reduction of 95.34% compared with the conventional capacitor switching scheme for CDACs. With the switching scheme, the ADC can lower the dependency on the accuracy of V_cm and complexity of DAC control logic and DAC driver circuit. Moreover, dynamic circuits and automatic ON/OFF technology are used to reduce power consumption of comparator and SAR logic. The prototype is designed and fabricated in a 180 nm CMOS with a core size of 500 μm × 300 μm (0.15 mm²). It consumes 7.6 nW at 1 kS/s sampling rate and 1.8-V supply with an achieved signal-to-noise-and distortion ratio of 45.90 dB and a resulting figure of merit of 51.7 fJ/conv.-step.

A DAC switching scheme that combines energy efficiency and resolution reconfigurability is proposed. Compared with the conventional switching scheme, the proposed scheme achieves 93.8%, 96.1%, and 97.3% switching energy saving in 8-bit, 9-bit, and 10-bit modes, respectively. Based on the proposed switching scheme, an 8–10-bit resolution-reconfigurable SAR ADC for biosensor applications is designed. The ADC consists of resolution-reconfigurable binary-weighted capacitive DAC, a two-stage full dynamic comparator, sampling switch, and the resolution-control SAR logic. Simulated in 180 nm CMOS process and 100 kS/s sampling rate, the ADC achieves the 46.80/53.89/60.14 dB signal-to-noise and distortion ratio (SNDR), the 55.22/62.51/73.09 dB spurious-free dynamic range (SFDR) and the 0.81/0.91/1.01 μW power consumption in 8/9/10-bit mode, respectively.

Three-color electrophoretic displays (EPDs) have the characteristics of colorful display, reflection display, low power consumption, and flexible display. However, due to the addition of red particles, response time of three-color EPDs is increased. In this paper, we proposed a new driving waveform based on high-frequency voltage optimization and electrophoresis theory, which was used to shorten the response time. The proposed driving waveform was composed of an activation stage, a new red driving stage, and a black or white driving stage. The response time of particles was effectively reduced by removing an erasing stage. In the design process, the velocity of particles in non-polar solvents was analyzed by Newton’s second law and Stokes law. Next, an optimal duration and an optimal frequency of the activation stage were obtained to reduce ghost images and improve particle activity. Then, an optimal voltage which can effectively drive red particles was tested to reduce the response time of red particles. Experimental results showed that compared with a traditional driving waveform, the proposed driving waveform had a better performance. Response times of black particles, white particles and red particles were shortened by 40%, 47.8% and 44.9%, respectively.

The shortage of color in traditional electrophoretic displays (EPDs) can be compensated by three-color EPDs. However, the response time of black particles and white particles is increased. A new driving waveform based on the principle of three-color EPDs and electrophoresis theory was proposed to shorten the response time of black particles and white particles. The proposed driving waveform consisted of an erasing stage, an activation stage, a red driving stage, and a white or a black driving stage. The activation stage was mainly optimized in this paper. Firstly, the motion characteristics of the particles were analyzed using Stokes law and electrophoresis theory. Secondly, an optimal high frequency oscillation voltage was tested in order to improve the activity of the particles. Then, the influence of oscillation period and oscillation times on the activation stage were analyzed for optimizing the reference grayscale. According to the luminance of pixels, an oscillation period of 30 ms and an oscillation time of 30 were determined. The experimental results showed that the response time of black particles was shortened by 45%, and the response time of white particles was shortened by 40% compared with a traditional driving waveform.

As an atomically thin semiconductor, 2D molybdenum disulfide (MoS₂) has demonstrated great potential in realizing next-generation logic circuits, radio-frequency (RF) devices and flexible electronics. Although various methods have been performed to improve the high-frequency characteristics of MoS₂ RF transistors, the impact of the back-gate bias on dual-gate MoS₂ RF transistors is still unexplored. In this work, we study the effect of back-gate control on the static and RF performance metrics of MoS₂ high-frequency transistors. By using high-quality chemical vapor deposited bilayer MoS₂ as channel material, high-performance top-gate transistors with on/off ratio of 10⁷ and on-current up to 179 μA/μm at room temperature were realized. With the back-gate modulation, the source and drain contact resistances decrease to 1.99 kΩ∙μm at V_bg = 3 V, and the corresponding on-current increases to 278 μA/μm. Furthermore, both cut-off frequency and maximum oscillation frequency improves as the back-gate voltage increases to 3 V. In addition, a maximum intrinsic f_max of 29.7 GHz was achieved, which is as high as 2.1 times the f_max without the back-gate bias. This work provides significant insights into the influence of back-gate voltage on MoS₂ RF transistors and presents the potential of dual-gate MoS₂ RF transistors for future high-frequency applications.