Fumito Imura

Reliability of a laser-via formation process for Fan-Out Wafer Level Packaging (FOWLP) technology was evaluated using Minimal Fab (MF) that is cleanroom-less and uses a half inch wafer. After a die-bonding and a compression molding process of a half-inch Si wafer, the laser-vias were formed with a diameter of 150 μm by irradiation of an ultra-violet (UV) pulsed laser beam. The measured thickness of the epoxy mold compound (EMC) was 93.9 μm of average with 1.9% of the variation at 1 σ in the half-inch wafer. The bottom diameter of the vias was 51.8 μm and 9.0% of the variation at 1 σ. In order to evaluate the contact-resistance of the vias, Cross-Bridge Kelvin Resistor (CBKR) test-structures were fabricated by the die-bonding the Si wafer with Al or Cu/Ti pads to a 42 alloy substrate, the compression molding, the laser-via, and the redistribution layer (RDL) formation. In case of the Al pads, the via conduction was obtained only in the outer peripheral area. On the other hand, in case of the Cu/Ti pad, the all via conductions were obtained. The high-yield via-interconnections were achieved by using Cu/Ti pads.

A Ball Grid Array (BGA) packaging tool-set and packaging process using a half-inch sized package have been developed. The packaging tool-set is integrated with device manufacturing process line of Minimal Fab that uses half-inch wafers. The packaging line for the half-inch sized package with packaging tools of a die-bonding, a compression molding, a laser ablation, a sputtering and an electroplating of Cu, a redistribution layer (RDL) patterning, a Cu wet-etching, an inkjet, a ball mounting, and a reflow were developed. The packaging process was evaluated by cross-bridge Kelvin resistor (CBKR) test-structures with 3-vias using the BGA package fabricated by the line. Moreover, we have improved electrical contacts between devices and the package by changing Al-Si electrode pads on the device to Cu/Ti pads. As a result, via contact-resistances of the vias with the Cu/Ti electrode pads have reduced by three orders of magnitude than those of the Al-Si electrode pads.

In this paper we present “Cool Interconnect,” a 1024-bit wide bus that we have developed to provide a standardized method of interconnecting chips in 3D integrated circuits (3DICs.) This wide bus chip-to-chip interconnect can be used to realize low-power high-performance multi-core systems to meet the increasing demand for advanced electronics to enable autonomous vehicles and Internet of Things (IoT) devices. The bus has been implemented using a 40×40 fine-pitch array of through-silicon vias (TSVs) and bump joints. Additionally, we have developed a testing methodology based on the boundary scan method to confirm the electrical performance of wide bus chip-to-chip interconnect in 3DICs. Cool Interconnect test chips were designed, fabricated and flip-chip stacked. JTAG and electrical connection tests were used to confirm the successful operation of the test chips, including the chip-to-chip interconnect.

We have developed a novel packaging tool-set of 13 machines to support continuous manufacturing process from a half-inch wafer process line until ready to be used. The packaging tools are made under minimal fab standard so that a half-inch wafer can be attached on a metal-substrate without dicing. The method that we employed is a BGA (Ball Grid Array)-type solder array which consists of following processes; a compression molding, a laser via, a copper redistribution layer (RDL) patterning, a solder-ball mounting, and a reflow. The development of each machine process and the total packaging process integration has been carried out. In this paper, we introduce a BGA packaging result using only our newly developed tools.

In this paper, we introduce our developed clean-localized system for a cleanroom-free semiconductor manufacturing where a wafer is air-tightly transferred between the carrier and the machine via a load port and process in a clean chamber. The system has been applied to “minimal fab” specially designed to process a half-inch wafer for low-cost and low-volume device productions. To confirm the localized clean-performance of our system, we have measured the clean levels in process chamber of a machine and the wafer transfer system. Both are resulting in ISO class 4, while the clean level of the circumstance is in ISO class 9. In order to estimate the system performance in the issue of electronic device properties, we fabricate a traditional MOSFET using minimal fab for the entire process. The measured density of interface states (Dit) of the MOSFET was 7.7×1010 cm ^-2 and the off-leak current was 4×10 ^-12 A. These are sufficiently low to confirm the acceptable particle contamination level of the system which has less impact on the device characteristics. Due to a compact size of the minimal machine, the wafer transfer distance between processes is minimized. The process efficiency of the minimal fab in terms of wafer transfer time and wafer waiting time is also studied.

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large thermal gradients. It is crucial to understand the interaction between process parameters, such as wafer thickness, and the temperature profile in order to design high-performance 3DICs. In this paper we examine how the temperature profile of a single TSV bus driver/receiver is impacted by die thinning. Die thinning limits the ability for heat to diffuse into the wafer, however decreasing the capacitance of the TSV can decrease the driver's power leading to an overall lower working temperature. In this work we found that thinning the top wafer with TSVs from 100 μm to 25 μm allowed for up to a 65% decrease in the steady-state temperature rise of a TSV driver/receiver running at 500 MHz.

3D LSI chip stacking technology have been developed using cone shape Au micro bumps fabricated by nanoparticle deposition method. The cone shape bumps with less than 10 um diameter are suitable for a thermocompression bump joint process with low temperature and low load force. High yield micro bump joints can be obtained. In this study, the property evaluation of the cone shape bumps, and the cone shape bump joints were investigated in details. The collapsed bump height and the electrical resistance can be controlled by compression force. The low resistance (average 8.6 mΩ) bump joint with a 10 μm diameter cone shape Au bump was successfully achieved.

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large spikes in individual device temperatures. These “hotspots” must be carefully analyzed at design time to ensure that the device temperatures will not cause the circuit to malfunction, and to assess the device temperature's impact on the longevity of the circuit. In this paper we present a tool flow for capturing accurate per-transistor power values in standard cell designs to allow for detailed thermal analysis. After extracting power values, High Definition Power Blurring is used to analyze the thermal performance of the inter-chip communication bus of a “Cool Interconnect” chip.

We have developed a fabrication technology of fine-pitch cone shape Au bump array using nanoparticle deposition method for 3D LSI chip stacking. 1024-bit wide bus chip-to-chip interconnection circuit called Cool Interconnect has been also developed using fine-pitch bump joint array technology and precise flip chip bonding technology. Such a wide bus chip-to-chip interconnection is suitable instead of on-chip bus interconnection in multi-core architecture LSI system in order to achieve low power operation. We propose a testing approach to confirm the chip-to-chip interconnect electrical performance using scan path method and JTAG test method in 3D LSI chip stacking system. The preliminary data transmitting experiment of Cool Interconnect using designed, fabricated, and flip-chip stacked test LSI chips was successfully done under low power consumption with clock frequency of 50MHz.