Yu Peng

Phase difference estimation is a core component of measurement and calibration in multi-channel systems. For two channels with the same nominal frequency, a joint sinusoidal model with seven parameters is employed to estimate the phase difference, thereby mitigating estimation bias from minor frequency mismatches. The parameters are obtained by solving the least-squares (LS) problem via singular value decomposition (SVD). Analysis shows that when the system matrix has a high condition number (CN), matrix computations are prone to illconditioning, leading to numerical instability in the iterative process. To alleviate this problem, this paper derives a closed-form scaling factor that minimizes the system matrix CN while preserving the LS solution, thereby ensuring numerical stability. Based on different amplitude relationships between channels, the CN under coherent sampling can be optimized to the range of (14, 110). Simulation results show that the ill-conditioned risk of the original SVD-LS algorithm increases significantly as the CN enters the medium-to-high range. After introducing the scaling factor derived in this paper, the CN of the system matrix decreases significantly, the iterative stability and convergence rate are systematically improved, and the LS optimal solution remains unchanged.

This paper identifies critical inefficiencies in traditional waveform analysis architectures for memory recorders, where function-specific (FS) accelerators and centralized processing on FPGA incur severe development and service efficiency bottlenecks. FS accelerators for various waveform analysis kernels not only demand labor-intensive manual design, but also suffer from exponential FPGA compilation delays and decreased performance due to fine-grained resource contention. Besides, centralized architectures further exacerbate service latency through PXIe bandwidth contention during massive data transfers. To resolve these limitations, this paper proposes a general-purpose (GP) accelerator architecture that enables the acceleration of arbitrary built-in and user-defined waveform analysis kernels via three innovations: (1) A coarse-grained tile array that pre-combines fine-grained FPGA resources into programmable compute units with dynamic dataflow; (2) A heuristic compiler automating kernel-to-tile mapping through modulo routing resource graphs, eliminating manual design efforts; (3) Distributed deployment across acquisition board FPGAs, localizing computation to eliminate centralized data transfers. Implemented in a self-designed 14-acquisition-board memory recorder prototype, the GP accelerator demonstrates 920∼6670× of development efficiency enhancement and 8.5∼27.5× service efficiency improvement over centralized FS accelerators under multi-kernel scenarios.