Fanfan Meng

Ru is a promising candidate for future post-Cu interconnect metallization because of its short electron mean free path and barrier-free reliability. Here, we demonstrate epitaxial Ru thin films on CMOS-compatible AlN (0001)/Si (111) grown by physical vapor deposition. X-ray diffraction, Rutherford backscattering ion channeling, and transmission electron microscopy confirm the single-crystal nature of the Ru films with a honeycomb epitaxial relationship. The films exhibit low resistivity of 7.8 μΩ cm at 30 nm thickness and a high residual resistivity ratio of 11, approaching bulk Ru values and outperforming polycrystalline Ru and Cu in the ultrathin film regime. Additional epitaxial growth on 300 mm wafers establishes epitaxial Ru on AlN (0001)/Si (111) as a scalable, CMOS-compatible platform for low-resistivity interconnect metallization.

Strain‐mediated magnetoelectric (ME) heterostructures enable electric‐field control of magnetism and are promising for ultra‐low‐power spintronic logic. Yet achieving spatially selective, low‐voltage control in thin films and quantifying ME coupling across the full ferroelectric strain hysteresis remains challenging. Here, we investigate sub‐micrometer Ni/BPZT thin‐film devices with laterally patterned gates that localize in‐plane strain beneath the Ni stripe and modulate its magnetization. We use anisotropic magnetoresistance to measure magnetization changes across the ferroelectric loop under different magnetic bias fields. Combined with multiphysics strain simulations and micromagnetic modeling, this work establishes a quantitative framework that captures the convolution of ferroelectric strain hysteresis and magnetoelastic nonlinearities, revealing how the magnetization evolves with ferroelectric strain under different bias fields and providing critical insight for future energy‐efficient device design. The extracted coupling coefficient in linear range is 1.3 mT V ^{− 1} across a 700 nm gap, with a clear pathway to improving voltage efficiency through device scaling and establishing a scalable CMOS‐compatible platform for energy‐efficient spintronic devices.

It is envisaged that spintronic logic devices will ultimately be utilized in hybrid CMOS-spintronic systems where signal interconversion between magnetic and electrical domains via transducers takes place. This underscores the vital role of transducers in influencing the overall performance of such hybrid systems. This paper addresses the question: Can spintronic circuits based on Magnetic Tunnel Junction (MTJ) transducers outperform their state-of-the-art CMOS counterparts? To this end, we use the EPFL (École Polytechnique Fédérale de Lausanne) combinational benchmark sets, synthesize them in 7 nm CMOS and in MTJ transducer based spintronic technologies, and compare the two implementation methods in terms of Energy-Delay-Product (EDP). To fully utilize the technologies’ potential, CMOS and spintronic implementations are built upon standard Boolean and Majority Gates, respectively. For the spintronic circuits, we assumed that domain conversion (electric/magnetic to magnetic/electric) is performed by means of MTJs and the computation is accomplished by domain wall (DW)-based majority gates, and considered two EDP estimation scenarios: (i) Uniform Benchmarking, which ignores the circuit’s internal structure and only includes domain transducers’ power and delay contributions into the calculations, and (ii) Majority-Inverter-Graph Benchmarking, which also embeds the circuit structure, the associated critical path delay and energy consumption by DW propagation. Our results indicate that, for the uniform case, the spintronic route is better suited for the implementation of complex circuits with few inputs and outputs. On the other hand, when the circuit structure is also considered via majority and inverter synthesis, our analysis clearly indicates that in order to match and eventually outperform CMOS performance, MTJ transducers’ efficiency has to be improved by 3-4 orders of magnitude. While it is clear that for the time being the MTJ-based-spintronic way cannot compete with CMOS, further technological transducer developments may tip the balance, which, when combined with information non-volatility, may make spintronic implementation for certain applications that require a large number of calculations and have a rather limited amount of interaction with the environment.

Three-dimensional (3D) spintronic devices are attracting significant research interest due to their potential for both fundamental studies and computing applications. However, their implementations face great challenges regarding not only the fabrication of 3D nanomagnets with high quality materials, but also their integration into 2D microelectronic circuits. In this study, we developed a new fabrication process to facilitate the efficient integration of both non-planar 3D geometries and high-quality multi-layered magnetic materials to prototype 3D spintronic devices, as a first step to investigate new physical effects in such systems. Specifically, we exploited 3D nanoprinting, physical vapour deposition and lithographic techniques to realise a 3D nanomagnetic circuit based on a nanobridge geometry, coated with high quality Ta/CoFeB/Ta layers. The successful establishment of this 3D circuit was verified through magnetotransport measurements in combination with micromagnetic simulations and finite element modelling. This fabrication process provides new capabilities for the realisation of a greater variety of 3D nanomagnetic circuits, which will facilitate the understanding and exploitation of 3D spintronic systems.