Binbin Yang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Binbin Yang has a total of 7 co-authors. Here are the top co-authors by number of shared publications:
- Daniel Arumi
Pfizer S.L.U. Medical Department, Madrid, Spain
2 shared publications - Francesca Campabadal
Institut de Microelectrònica de Barcelona, IMB-CNM, CSIC 1 , Campus UAB, 08193 Cerdanyola del Vallès
2 shared publications - Liang Fang
National University of Defense Technology
2 shared publications - Mireia Bargallo Gonzalez
Institut de Microelectrònica de Barcelona
2 shared publications - Rosa Rodriguez-Montanes
Departament d’Enginyeria Electrònica, Universitat Politècnica de Catalunya, 08028 Barcelona, Spain
2 shared publications - Salvador Manich
Departament d’Enginyeria Electrònica, Universitat Politècnica de Catalunya, 08028 Barcelona, Spain
2 shared publications
Latest Publications
- Open Access
- 31 July 2021
- Published by MDPI AG in Electronics
- Vol. 10 (15) , 1842
Serial RRAM Cell for Secure Bit Concealing
Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal.
- 31 July 2021
- Published by MDPI AG in Electronics
- Vol. 10 (15) , 1842
Open AccessSerial RRAM Cell for Secure Bit Concealing
Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal.
- Open Access
- 30 July 2021
- Published by MDPI AG in Electronics
- Vol. 10 (15) , 1831
RRAM Random Number Generator Based on Train of Pulses
In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications.
- 30 July 2021
- Published by MDPI AG in Electronics
- Vol. 10 (15) , 1831
Open AccessRRAM Random Number Generator Based on Train of Pulses
In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications.