Peng Li

This article presents the design and implementation of a 40 MHz crystal oscillator (XO) with low phase noise, based on the 55 nm CMOS process, for wireless transceiver systems, particularly those used in Wireless Local Area Network (WLAN). The proposed design employs a bandgap reference circuit that includes a start-up circuit and a low-voltage common-source common-gate current mirror, which ensures that the bandgap reference circuit is powered up effectively across all temperatures and process corners. A low-pass filter is also incorporated at the low dropout regulator (LDO) input to reduce the phase noise of the XO circuit. The experimental results demonstrate that the proposed design achieves a final phase noise of −164.36 dBc/Hz at 100 kHz offset frequency, with a power consumption of 0.444 mW. The test of start-up time is 0.718 ms and the compact chip area is 0.088 mm². According to the simulation and test results, the final FOM value calculated in this paper is 209.93 dBc/Hz at 100 kHz offset.

This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

The demand for a local oscillator (LO) signal of high quality and integrity in local area network (WLAN) communication is growing with the increasing date rate. The LO signals for high data rate WLAN applications are desired to not only have proper shape waveforms and adequate voltage amplitude but also to achieve relatively stable and clean outputs with low phase noise and low spur. Fractional-N frequency planning is critical for a quadrature LO-generator, which is achieved by a single-sideband (SSB) mixer and multiple dividers since it can avoid the frequency pulling and alleviate the self-mixing and DC offset issues, while spur levels are easily increased due to harmonic mixing, imbalance, and leakage of the SSB mixer. This article proposes a simple and innovative quadrature LO-generator, which adopts a current-mode-logic (CML) inductive peaking (IP) circuit to improve phase noise and suppress spurious tones. Four types of LO delivery methods using IP circuits are proposed and compared. Among four methods, the CML-IP circuit presents the optimum performance for driving long wires of multi-mm length. Instead of previous digital spur cancellation, the CML-IP circuit achieves higher spur suppression, lower jitter, and a greater figure of merit (FoM). The quadrature LO-generator can be configured to either VCO mode or bypass mode supporting external VCO input. Implemented in 55 nm CMOS technology, the proposed quadrature LO-generator achieves −52.6 dBc spur suppression, −142 dBc/Hz phase noise at 1 MHz offset at the 4.8 GHz frequency, and −271 FoM. Furthermore, the quadrature LO-generator occupies an active area of 0.178 mm² and consumes 23.86 mW.