Minjae Kim

We demonstrate a pull-middle architecture for standard ternary inverters (STIs) operating at 77 K, enabled by the cointegration of a ZnO–Te antiambipolar switch (AAS) and vertically stacked ZnO/Te complementary field-effect transistors (CFETs) using a BEOL-compatible low-temperature process (≤150 °C). Operation at 77 K not only isolates the intrinsic pull-middle switching mechanism by suppressing thermally activated off-currents but also establishes the architecture’s immediate viability for extreme-environment computing, such as radiation-hardened space data centers and cryogenic aerospace systems. In this architecture, the ZnO–Te AAS acts as an independent pull-middle device connected to an explicit Vdd/2 node, while the ZnO and Te FETs in the CFET serve as the pull-down and pull-up devices, respectively. Unlike conventional ternary logic schemes governed by precise pull-up/pull-down current matching, by explicitly clamping the intermediate state, this architecture structurally prevents variation-induced voltage shifts and suppresses static power dissipation. Consequently, the proposed STI exhibits a narrow middle-state voltage distribution across 25 cells and achieves an I/O swing ratio of 1, with cascaded operation without level-restoring circuitry supported by measurement-calibrated circuit simulations. Ultimately, this vertically integrated ZnO/Te STI offers a compact and variation-tolerant platform for cryogenic logic, while presenting a material-optimization pathway toward room-temperature multivalued systems.

Tellurium (Te) is increasingly gaining attention as a scalable p-type channel material owing to its inherently high carrier mobility and ambient stability. However, in sub-5 nm Te channels, high contact resistance remains a major obstacle to achieving high-performance device operation. In this study, an estimated contact resistance of ≈1.7 kΩ·μm is obtained in 4 nm-thick Te channels by engineering the band structure in the source and drain (S/D) regions using a raised source and drain (RSD) structure. To isolate intrinsic contact behavior, electrical measurements are conducted at 77 K, in which thermally activated defect states are suppressed, and carrier injection is dominated by the metal-semiconductor interface. Transport characterization reveals a more than 17-fold increase in on-state current and a more than 50-fold reduction in contact resistance relative to Te devices without the RSD structure. This enhancement is attributed to selectively increasing the Te thickness at the S/D terminals, which tunes the bandgap by thickness-dependent modulation. The resulting RSD architecture enhances tunneling current by narrowing the barrier width─modulated by gate bias. This scalable, low-temperature approach offers broad applicability to other ultrathin channel materials.

This study identifies the origin of excess low-current noise in ultrathin Te FETs and suppresses it by locally modulating the Te thickness near the contacts.

Combinations of n- and p-type semiconductors (with thicknesses of a few nanometers or ultrathin) deposited at low temperatures are creating new opportunities for novel devices and circuits. We demonstrate an antiambipolar switch (AAS) device using a heterojunction comprising extremely thin ZnO and Te layers operating at a complementary metal-oxide semiconductor (CMOS)-compatible bias (∼1.2 V) with a high peak-to-valley ratio (∼10⁴). The entire process was performed at a full wafer scale with a low thermal budget at temperatures below 150 °C. The device count and area of the binary-to-ternary converter designed with this device were reduced by ∼95% and ∼97%, respectively. In addition, we demonstrate a few examples of binary-ternary logic circuits to show that the system complexity and computing efficiency of the binary CMOS architecture can be dramatically improved by easily cointegrating the ZnO-Te AAS-based converter in the back-end-of-line structure.

A novel approach to delicately control the phase of a ferroelectric has been developed using a continuous-wave laser scanning annealing (CW-LSA) process. After proper process optimization, the equivalent oxide thickness (EOT) of 3.5 Å with a dielectric constant (κ) of 68 Å is achieved from HZO in a metal-ferroelectric-metal (MFM) capacitor structure. The leakage current density (J_g = 4.6 × 10^-5 A/cm² at +0.8 V) was four times lower compared to the reference group treated with an optimized RTA process. The outstanding electrical characteristics of the 6 nm HZO film were attributed to the stable formation of the morphotropic phase boundary (MPB) structure, which was enabled by the directional scanning nature of the CW-LSA process.

This study proposes an ultrathin tellurium (Te) atomic layer deposition process with a TeO _x seed layer to overcome large electrical hysteresis. It also identifies causes of defects, aiding high-performance p-type inorganic transistors.

This study investigates the switching characteristics of the silicon oxynitride (SiO_xN_y)-based bipolar resistive random-access memory (RRAM) devices at different operating ambiances at temperatures ranging from 300 K to 77 K. The operating ambiances (open air or vacuum) and temperature affect the device’s performance. The electroforming-free multilevel bipolar Au/Ni/SiO_xN_y/p⁺-Si RRAM device (in open-air) becomes bilevel in a vacuum with an on/off ratio >10⁴ and promising data retention properties. The device becomes more resistive with cryogenic temperatures. The experimental results indicate that the presence and absence of moisture (hydrogen and hydroxyl groups) in open air and vacuum, respectively, alter the elemental composition of the amorphous SiO_xN_y active layer and Ni/SiO_xN_y interface region. Consequently, this affects the overall device performance. Filament-type resistive switching and trap-controlled space charge limited conduction (SCLC) mechanisms in the bulk SiO_xN_y layer are confirmed.

This study investigates switching characteristics of the magnesium fluoride (MgF_x)-based bipolar resistive random-access memory (RRAM) devices at different operating ambiances (open-air and vacuum). Operating ambiances alter the elemental composition of the amorphous MgF_x active layer and Ti/MgF_x interface region, which affects the overall device performance. The experimental results indicate that filament type resistive switching takes place at the interface of Ti/MgF_x and trap-controlled space charge limited conduction (SCLC) mechanisms is dominant in both the low and high resistance states in the bulk MgF_x layer. RRAM device performances at different operating ambiances are also altered by MgF_x active layer treatments (air exposure and annealing). Devices show the better uniformity, stability, and a higher on/off current ratio in vacuum compared to an open-air environment. The Ti/MgF_x/Pt memory devices have great potential for future vacuum electronic applications.

Electroforming-free resistive switching random access memory (RRAM) devices employing magnesium fluoride (MgF_x) as the resistive switching layer are reported. The electroforming-free MgF_x based RRAM devices exhibit bipolar SET/RESET operational characteristics with an on/off ratio higher than 10² and good data retention of >10⁴ s. The resistive switching mechanism in the Ti/MgF_x/Pt devices combines two processes as well as trap-controlled space charge limited conduction (SCLC), which is governed by pre-existing defects of fluoride vacancies in the bulk MgF_x layer. In addition, filamentary switching mode at the interface between the MgF_x and Ti layers is assisted by O–H group-related defects on the surface of the active layer.