Zhiping Wang

The three-phase isolated ac-dc matrix converter (3P-IMC) inherits all the merits of the conventional matrix converter. But it also suffers from a large number of bidirectional switches and can not operate safely in open-circuit fault condition. Hence, with a general space vector PWM (SVPWM) model presented in this paper, three types of asymmetrical SVPWM (ASVPWM) schemes are first proposed for normal and open-circuit fault-tolerant operation. The ASVPWM schemes have more kinds of synthetic vectors with asymmetrical distribution, however, also features a higher freedom and flexibility to further improve the system performance. Then by sectional combining the above ASVPWM schemes with the conventional one, the 3P-IMC could be continued to operate with a tight dc output voltage regulation under single-switch open-circuit fault condition, which has an inherent open-circuit fault-tolerant capability. Compared with the conventional two-phase fault-tolerant operation, the proposed method has a smaller output voltage ripple, lower current stress, lower current harmonic and higher maximum output power, etc. The safety and reliability of the converter are greatly improved. Finally, a 3P-IMC experimental prototype is built up to verify the performance of the proposed ASVPWM schemes.

For a three-phase isolated AC-DC matrix converter, the slight volt-second imbalance caused by variable input voltage is an inherent defect and has been neglected in most PWM schemes. The analysis in this paper shows that the imbalance lies in a single direction during the entire input cycle, and it might generate a large DC bias to severely decrease the efficiency of the steady-state operation. Therefore, the imbalance phenomenon is first investigated, and the generation mechanism of the steady-state DC bias is derived in detail. To eliminate such a DC bias, a novel transformer primary-side voltage pulse is originally defined. Based on the special crisscrossing operation mode with the above pulse, a simple but effective four-segment space vector PWM (4S-SVPWM) scheme is proposed. Compared with the conventional more-segment SVPWM schemes, the novel 4S-SVPWM scheme can achieve volt-second self-balancing without auxiliary methods, as well as a 1/2 reduction in the common-mode voltage (CMV) peak value and a 1/3 reduction in the switching actions. The overall efficiency and power density of the converter are greatly improved. Finally, an experimental prototype is built to validate the correctness and effectiveness of the novel scheme.