Jaemin Kim

Understanding solid‐state graphitization is critical for the low‐temperature synthesis of ultrathin graphene with controlled thickness and morphology. Here, we directly reveal the graphitization mechanism of a Ru–Ni bimetallic thin‐film catalyst using in situ transmission electron microscopy, complemented by theoretical calculations. Unlike conventional Ni catalysts, in which graphene growth is mediated by Ni ₃ C formation and decomposition, Ru alloying suppresses detectable carbide formation across all investigated alloy compositions under the present conditions and promotes a surface‐diffusion‐dominated graphitization pathway distinct from that of pure Ni. The Ru–Ni 1:1 ratio catalyst exhibits enhanced thermal stability at ∼650°C, enabling graphene formation prior to catalyst diffusion and yielding an ultraflat nanocrystalline graphene film from an ultrathin catalyst/precursor stack. In situ electron diffraction and electron energy loss spectroscopy precisely identify the onset of graphene formation, while compositional tuning reveals growth behavior that fundamentally differed with pure Ni, even in Ni‐rich alloys. Density functional theory calculations confirm that carbide phases are thermodynamically unfavorable in Ru–Ni alloys, supporting a surface‐diffusion‐dominated growth mechanism analogous to that of Cu. These findings establish a new catalyst design rule for low‐temperature synthesis of ultrathin and flat graphene.

Two‐dimensional (2D) memristors are promising for low‐power and high‐speed neuromorphic hardware. However, their performance under circuit‐level constraints remains limited because resistive switching relies on native defects, hindering precise control of filament formation. Here, we report 2D MoTe ₂ memristors that integrate deterministic switching‐path density engineering with CMOS‐compatible one‐transistor‐one‐memristor (1T‐1 M) architectures. The devices exhibit highly linear and symmetric synaptic plasticity (α _p /α _d = 0.019/0.2), enabled by a balanced interplay between filament formation and confinement. Furthermore, monolithic integration with silicon transistors enables gate‐tunable compliance control, which suppresses variability and stabilizes array‐level operation. The resulting 1T‐1 M arrays exhibit a wide dynamic range (∼22×), and minimal potentiation/depression variation (7.95%/6.22%). Device‐aware simulations based on multilayer perception, convolutional neural network, and autoencoder models confirm improved learning accuracy compared to passive arrays. This work establishes a materials‐to‐circuit design framework that links defect‐path engineering with transistor‐assisted current control, providing a practical pathway toward 2D neuromorphic hardware.