Yuxuan Hou
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Yuxuan Hou has a total of 12 co-authors. Here are the top co-authors by number of shared publications:
- Wei Chen
Zhejiang University, Hangzhou, Zhejiang, China
2 shared publications - Kaiyuan Zhang
Zhejiang University
1 shared publication - Liangjun Liu
Zhejiang University
1 shared publication - Minfeng Zhu
Zhejiang University, Hangzhou, Zhejiang, China
1 shared publication - Qiming Hou
State Key Lab of CAD & CG, Zhejiang University, Hangzhou, China
1 shared publication Wei Chen
The First Affiliated Hospital, Zhejiang University, Hangzhou, China
1 shared publication
Latest Publications
- 12 July 2023
- Published by Springer Nature in The Visual Computer
- Vol. 39 (8) , 3783-3796
InstantTrace: fast parallel neuron tracing on GPUs
- 12 July 2023
- Published by Springer Nature in The Visual Computer
- Vol. 39 (8) , 3783-3796
InstantTrace: fast parallel neuron tracing on GPUs
- 16 September 2021
- Published by Zhejiang University Press in Frontiers of Information Technology & Electronic Engineering
- Vol. 22 (9) , 1169-1178
Learning-based parameter prediction for quality control in three-dimensional medical image compression
Quality control is of vital importance in compressing three-dimensional (3D) medical imaging data. Optimal compression parameters need to be determined bas
- 16 September 2021
- Published by Zhejiang University Press in Frontiers of Information Technology & Electronic Engineering
- Vol. 22 (9) , 1169-1178
Learning-based parameter prediction for quality control in three-dimensional medical image compression
Quality control is of vital importance in compressing three-dimensional (3D) medical imaging data. Optimal compression parameters need to be determined bas
- 4 December 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Visualization and Computer Graphics
- Vol. 27 (2) , 1666-1676
DRGraph: An Efficient Graph Layout Algorithm for Large-scale Graphs by Dimensionality Reduction
Efficient layout of large-scale graphs remains a challenging problem: the force-directed and dimensionality reduction-based methods suffer from high overhead for graph distance and gradient computation. In this paper, we present a new graph layout algorithm, called DRGraph, that enhances the nonlinear dimensionality reduction process with three schemes: approximating graph distances by means of a sparse distance matrix, estimating the gradient by using the negative sampling technique, and accelerating the optimization process through a multi-level layout scheme. DRGraph achieves a linear complexity for the computation and memory consumption, and scales up to large-scale graphs with millions of nodes. Experimental results and comparisons with state-of-the-art graph layout methods demonstrate that DRGraph can generate visually comparable layouts with a faster running time and a lower memory requirement.
- 4 December 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Visualization and Computer Graphics
- Vol. 27 (2) , 1666-1676
DRGraph: An Efficient Graph Layout Algorithm for Large-scale Graphs by Dimensionality Reduction
Efficient layout of large-scale graphs remains a challenging problem: the force-directed and dimensionality reduction-based methods suffer from high overhead for graph distance and gradient computation. In this paper, we present a new graph layout algorithm, called DRGraph, that enhances the nonlinear dimensionality reduction process with three schemes: approximating graph distances by means of a sparse distance matrix, estimating the gradient by using the negative sampling technique, and accelerating the optimization process through a multi-level layout scheme. DRGraph achieves a linear complexity for the computation and memory consumption, and scales up to large-scale graphs with millions of nodes. Experimental results and comparisons with state-of-the-art graph layout methods demonstrate that DRGraph can generate visually comparable layouts with a faster running time and a lower memory requirement.