Bjorn Vermeersch

This article presents an electrothermal model for a InGaAs/GaAs quantum well (QW) nanoridge (NR) laser diode monolithically integrated in a Si photonics wafer. Heat conduction inside the laser is modeled using both the finite element (FE) method and the Boltzmann transport equation (BTE) for phonon transport. The BTE model captures nanoscale thermal effects and is used to calibrate the FE model, which captures large-scale effects, such as heat spreading in the Si substrate. Two methods are used to obtain the power distribution inside the laser: first, electrical TCAD simulation is carried out for the p-i-n structure and second, an equivalent electrical circuit is extracted from measurement data. The simulation results of the different thermal and electrical models are compared and finally experimentally validated using spectral measurements. We conclude that the simulated laser thermal resistance ${R}_{\text {th, {sim}}}={74}\pm {8}.{9}$ mm-K/W is in good agreement with the experiments ${R}_{\text {th, {exp}}}={78}.{2}\pm {15}.{2}$ mm-K/W; furthermore, the model predicts a local hot spot at the p-contact, which is a bottleneck for laser reliability. This insight will drive future design iterations.

In this paper, we introduce a modular thermal modeling methodology, BTE-FEM, that combines the Boltzmann Transport Equation (BTE) with Finite Element Modeling (FEM) for simulations of advanced back-end-of-line (BEOL) stacks with high accuracy and efficiency. BTE-FEM is validated against direct BTE-based simulations using simplified BEOL stack test cases across various technology nodes and via connectivity configurations. It is demonstrated that conventional FEM, using bulk material properties, increasingly underestimates the BEOL thermal resistance as the technology node scales. In contrast, the BTE-FEM developed in this study demonstrates good agreement with direct BTE simulations for all test cases, but at much shorter runtimes. The impact of material properties, metal densities, and boundary conditions on the derived BEOL thermal properties are benchmarked and the developed models are experimentally validated at two distinct technology nodes. Finally, the developed methodology is applied to a 12-layer, 18 nm metal pitch BEOL stack from an A10 high density core design, demonstrating its ability to simulate complex and realistic BEOL routings with the precision of direct BTE simulations while substantially reduced simulation time. This approach enables extensive Design of Experiments (DOE) for fast turnaround design iterations.

Due to the rise in the number of cores in modern multicore architectures, 3-D integration (i.e., vertical stacking of chips) of system-on-a-chip (SOC) promises better performance due to a drastic reduction in global interconnect lengths and die footprint compared with 2-D counterparts. However, thermal issues are predominant in 3-D-SOCs due to the vertical stacking nature of chips which multiplies the transistor power density by the number of dies within the stack. Also, the reduced lateral heat spreading with aggressive die thinning degrades the on-chip thermal performances. In this article, we investigate the thermal performance analysis of 3-D-SOC and compare the results with the 2-D-SOC designs for a MemPool multicore SOC with shared L1 scratchpad memory (SPM). Simulation results reveal that the 3-D-SOC using memory-on-logic (MOL) configuration increases the on-chip maximum temperature by more than 20% compared with the baseline 2-D-SOC and the logic die temperature is relatively higher (3.6%) than the memory die. We also explore the impact of architectural floor-planning effects and 3-D functional partitioning on thermal performance of the MemPool instances in the 3-D-SOC with memory capacity ranging from 1 to 8 MiB and benchmarked the thermal performance with the 2-D-SOC designs. We observe that the junction-to-ambient temperature ( $T_{\max}$ ) increases by 44% and is predominant for the SPM capacity of 8 MiB. Further investigations on various 3-D stacking configurations reveal there is an improvement in thermal performance for MOL over logic-on-memory (LOM) for L1 SPM capacity of 1, 2, and 4 MiB, and LOM over the MOL configuration for L1 SPM capacity of 8 MiB.

The presence of multiple cores in modern multicore architectures makes thermal management and temperature estimation a really challenging task for enhancing reliability and lifespan. Due to the presence of many cores, the core/tile spacing needs to be optimized in order to enhance the thermal coupling between interconnect routing blocks and active tiles. In addition, the tiles activity patterns under partial workload conditions significantly affect the maximum on-chip temperature which results in nonuniform temperature distribution. This is due to poor thermal coupling between neighboring tiles owing to the decrease in spacing between cores. In this article, we investigate the thermal performance analysis of a 256-core (i.e., 64 tiles) Mempool reduced instruction set computer (RISC) V-based architecture considering the impact of inter tiles spacing. Simulation results reveal that lateral heat spreading predominantly affects the thermal performance in multicore architectures under partial workload conditions. We also optimize the thermal performance with different tiles activity pattern. Simulation results reveal that both the maximum on-chip temperature and lateral heat spreading are improved for specific tiles activity patterns. Also the thermal performance analysis considering the “tile-insite effect” reveals that there is little impact on on-chip maximum temperature ( $T_{\text{max}}$ ), but the on-chip thermal gradient ( $\Delta T$ ) and the thermal profile pattern are predominantly affected. Finally, the effect of the secondary heat path toward printed circuit board (PCB) is studied in this work.

This paper benchmark the intrinsic trade-off between two essential modules of gate-all-around GAA nanosheet (NS)FETs viz. inner-spacers (ISPs) epi-induced stress in the channel. While having both ISPs and the stress is the best-case scenario for NSFET, it comes with enhanced process challenges and performance risks: poor epi-quality resulting in a no-channel stress scenario. While inner-spacers are important to parasitic capacitance reduction, we show that having intrinsic epi-stress is more beneficial and provides a better performance trade-off. We further evaluate the impact of inner-spacer κ-value and enhanced epi-volume for the two different cases. Finally, we have performed self-heating studies to show how skipping inner-spacers can provide additional reduction in peak temperature.

Electrical four-terminal sensing at (sub-)micrometer scales enables the characterization of key electromagnetic properties within the semiconductor industry, including materials’ resistivity, Hall mobility/carrier density, and magnetoresistance. However, as devices’ critical dimensions continue to shrink, significant over/underestimation of properties due to a by-product Joule heating of the probed volume becomes increasingly common. Here, we demonstrate how self-heating effects can be quantified and compensated for via 3ω signals to yield zero-current transfer resistance. Under further assumptions, these signals can be used to characterize selected thermal properties of the probed volume, such as the temperature coefficient of resistance and/or the Seebeck coefficient.