Sanguk Lee

In perpendicular spin–orbit torque (SOT) magnetic random-access memory, the SOT-track and the perpendicular magnetic tunnel junction (pMTJ) stack are typically deposited sequentially without vacuum break to minimize interfacial contamination. However, this requirement fundamentally limits interface engineering between the SOT-track and pMTJ, restricting independent optimization of each module and reducing process flexibility. This study demonstrates an in situ surface etching-assisted deposition (ISED) process that enables efficient interface engineering without sacrificing interfacial integrity. By integrating ion beam etching (IBE) and magnetron sputtering within a single vacuum system, the ISED process decouples the deposition of the SOT-track and pMTJ stack, enabling integrated module-level optimization. We demonstrate the ISED process using a β-W/CoFeB/MgO/Ta heterostructure. The IBE process effectively smoothed the β-W surface under optimized etching conditions, reducing surface roughness by 30.1%. Consequently, the ISED stack revealed a clear and smooth interface, leading to improved MgO crystallinity compared with the stack without ISED. The x-ray-based analyses confirmed that the ISED process modifies crystallinity and bonding of the β-W surface, reducing interface contamination and enhancing β-W/CoFeB bonding. The magnetic characterizations confirmed perpendicular magnetic anisotropy (PMA) in ISED-processed stacks, both in the as-deposited sample and after annealing, even at sub-nanometer (down to 5 Å) CoFeB thicknesses. Moreover, ISED-processed stacks exhibited PMA after the β-W layer was exposed to ambient air prior to CoFeB/MgO deposition, underscoring its effective surface plasma cleaning capability.

This study comprehensively investigated dielectric wall line edge roughness (LER)-induced dc/ac performance variabilities in forksheet (FS) field-effect transistors (FSFETs) using 3-D technology computer-aided design. In addition, we proposed a novel method based on the error propagation law to analyze RC delay variability in advanced devices, revealing a unique variability compensation effect in FSFETs. Although the dielectric wall in the FSFETs enables further scaling, its process difficulty is expected to increase LER and lead to variability degradation. The results showed that FSFETs exhibit greater variability in dc/ac performance than naonsheet (NS) FETs (NSFETs). This is, primarily because of the larger LER in FSFETs, caused by the smaller critical dimension of the dielectric wall. Furthermore, the impact of LER on structural parameters becomes more pronounced as the number of stacks increases, further exacerbating performance variabilities. Nevertheless, FSFETs exhibit compensation in RC delay variability, which is a key metric for digital logic applications, owing to the strong correlation between on-state current ( $\textit{I}_{\text {on}}$ ) and gate capacitance ( ${C}_{\text {gg}}$ ). This effect alleviates the performance variations observed in each of the dc/ac performance metrics at the RC delay stage. Therefore, it is revealed that the dielectric wall of the FSFETs does not cause significant degradation in variability.

For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of horizontal FET (HFET) which are nanosheet FET (NSFET) and forksheet FET (FSFET) targeting Angstrom nodes. The conventional VFET (VFETCON) design exhibits a larger footprint than FSFET, delivering an inferior performance even when optimized for gate length. By contrast, the novel fork-shaped channel VFET (VFETFS) demonstrates a 10.5% reduction in the effective area compared to VFETCON, achieving a smaller footprint than FSFET with a large contact poly pitch (CPP). Additionally, $\mathrm { VFET_{FS}}$ offers enhanced performance over $\mathrm { VFET_{CON}}$ due to reduced capacitance. However, $\mathrm { VFET_{FS}}$ shows more effective area and has a significantly lower drive current (Ion) than FSFET with a small CPP. Strategies to expand the silicide area effectively improve $\mathrm { I_{on}}$ by reducing parasitic resistance, enabling NFET $\mathrm { VFET_{FS}}$ to outperform FSFET. However, for PFET, $\mathrm { VFET_{FS}}$ employing enlarged silicide areas exhibits lower performance compared with FSFET owing to the more substantial impact of performance degradation under non-stress conditions. The secondary device architecture, $\mathrm { VFET_{FS}}$ with back-side contact (VFETBSC), further decreases the footprint, significantly lowers parasitic RC, and shows great heat dissipation when it has a large BSC area. $\mathrm { VFET_{BSC}}$ requires a smaller effective area than FSFET with a 42 nm CPP, and its average performance for N/PFET surpasses that of FSFET.

For the first time, this study investigated the standard cell and chip-level power, performance, and area (PPA) benefit of ultra-stacked forksheet-FET (FSFET) with five channels for Angstrom nodes. Five-stack FSFET shows a smaller channel width than conventional four-stack FSFET at the same drive current condition, enabling additional scaling. In conventional nanosheet-FET (NSFET), a large number of channels increases parasitic resistance and capacitance, which degrades device performance. However, the wall of FSFET, the wrap-around contact, the metal source/drain, and the small vertical spacing of the channel can mitigate the increases in parasitics. Therefore, a five-stack FSFET can achieve a small footprint without frequency degradation. We developed 4T standard cells with heights of 76 and 68 nm for four-stack FSFET and five-stack FSFET, respectively. In the same device performance condition, the five-stack FSFET-based cells show a smaller energy-delay product due to the small capacitance. Five-stack FSFET-based chip shows a 10.5%~10.7% smaller area and 7.0%~7.5% shorter wire length for all benchmarks. The shorter wire length reduces wire capacitance; thus, the five-stack FSFET-based chip shows a smaller power consumption. On the other hand, the five-stack FSFET has a smaller metal width and a larger wire resistance. However, the five-stack FSFET-based chip shows only a slight increase in power-delay product (PDP) due to the gate-dominated circuit, great optimization using buffer insertion, and a backside power delivery network (BS-PDN). Overall, the five-stack FSFET-based chip shows only a slightly degraded PDP with 10.5%~10.7% smaller area. Ultra-stacked FSFET enables additional scaling, with only an increase in channel number before adopting complementary-FET (CFET).

In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. In contrast, forksheet FETs (FSFETs) enable aggressive CH reduction by introducing a dielectric wall between N/P-type devices. However, FSFETs have inherent drawbacks: one side of the channel and source/drain (S/D) inevitably interfaces with the wall, leading to a compromised electrical performance compared with that of NSFETs. Moreover, when the gate edge aligns with the wall on one side, sufficient GE and GC margins are still required on the opposite side. To address these challenges, we propose patterned multi-wall NSFETs (MW-NSFETs) comprising patterned walls on both sides of the channel, which facilitate gate-all-around channel formation and wrap-around contact, resulting in superior DC behavior. Furthermore, CH can be scaled down as both sides of the gate edges self-align with the patterned multiwall. Consequently, MW-NSFETs yield a higher I_on (4.65%) and lower RC delay (6.2%) at a 12.04% smaller CH than FSFETs. Moreover, at the circuit level, the MW-NSFETs exhibited a higher oscillation frequency compared with FSFETs. Thus, MW-NSFETs represent viable devices for sub-2-nm nodes, meeting the stringent criteria for high performance and minimal CH values in logic applications.

We present a novel multi-task learning (MTL) approach with shared representation for the real-time extraction of Berkeley Short-channel IGFET Model-Common Gate (BSIM-CMG) parameters in nanosheet field-effect transistors (NSFETs) with multiple structural variations. An innovative artificial neural network (ANN) architecture, coupled with specialized training strategies, was introduced to extract BSIM-CMG parameters in NSFETs with varying gate lengths ( L _g ), nanosheet widths ( W _ns ), and thicknesses ( T _ns ). To mitigate overfitting due to disparate data sources, such as Monte Carlo simulations for training data and technology computer-aided design (TCAD) simulations or hardware measurements for test data, additive noise was incorporated into the training data. Optimal test accuracy was achieved with maximum noise levels of 10% for I _d and 2% for C _gg . The MTL approach, leveraging shared representation, effectively captured relationships among input-output groups, reducing the risk of biased ANN training toward any specific group. The proposed method was evaluated using a 1.4 nm node TCAD NSFET and eight additional NSFETs with L _g , T _ns , and W _ns variations of 1, 0.5, and 5 nm, respectively, from the baseline values of 12, 5, and 25 nm at the 1.4 nm node. The MTL-based ANN successfully extracted BSIM-CMG parameters for both I _d and C _gg , yielding low relative modeling errors of 4.26% for I _d and 0.709% for C _gg . Additionally, the method was validated using 3 nm node hardware NSFETs and nanowire FETs with varying L _g and nanowire diameters, demonstrating its versatility across different technology nodes and device architectures.