Ruibo Wang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Ruibo Wang has a total of 5 co-authors. Here are the top co-authors by number of shared publications:
- Xianyang Jiang
School of Physics and Technology, Wuhan University, Wuhan 430072, China
2 shared publications - Yiyang Zhao
School of Physics and Technology, Wuhan University, Wuhan 430072, China
1 shared publication - Yongjia Wang
School of Physics and Technology, Wuhan University, Wuhan 430072, China
1 shared publication - Yu Jia
School of Physics and Technology, Wuhan University, Wuhan 430072, China
1 shared publication - Yuan Rong
School of Physics and Technology, Wuhan University, Wuhan 430072, China
1 shared publication
Latest Publications
- Open Access
- 7 January 2024
- Published by MDPI AG in Electronics
- Vol. 13 (2) , 271
A Real-Time Image Stitching and Fusion Algorithm Circuit Design Based on FPGA
In the widely used field of panoramic image stitching, the key technologies mainly cover two parts, i.e., image registration and image fusion. In order to achieve low-cost and real-time processing, researchers often design dedicated circuits for various image stitching algorithms. Many studies focus on image registration algorithms and ignore image fusion algorithms, let alone dedicated circuit design. In addition, to reduce the ghosting effect and deformation caused by seams in stitching, finding the best seam line based on the overlapping area of the stitching image is crucial, which directly affects the quality of image stitching and fusion. In order to solve the above problems and achieve the efficient fusion of registered images, an image stitching and fusion algorithm circuit based on a dynamic programming algorithm to search for seam lines was proposed. Comprehensive experimental results and a theoretical analysis based on Cyclone IV FPGA devices show that, with a clock frequency of 100 MHz, the proposed circuit takes about 7.04 ms to carry out the fusion processing of two 486 × 643 images, and the corresponding frame rate is approximately 142 FPS, achieving a perfect real-time stitching effect and meeting the demand for real-time image processing. After a theoretical derivation and comparison with other similar works, its processing speed is better than four state-of-the-art implementations.
- 7 January 2024
- Published by MDPI AG in Electronics
- Vol. 13 (2) , 271
Open AccessA Real-Time Image Stitching and Fusion Algorithm Circuit Design Based on FPGA
In the widely used field of panoramic image stitching, the key technologies mainly cover two parts, i.e., image registration and image fusion. In order to achieve low-cost and real-time processing, researchers often design dedicated circuits for various image stitching algorithms. Many studies focus on image registration algorithms and ignore image fusion algorithms, let alone dedicated circuit design. In addition, to reduce the ghosting effect and deformation caused by seams in stitching, finding the best seam line based on the overlapping area of the stitching image is crucial, which directly affects the quality of image stitching and fusion. In order to solve the above problems and achieve the efficient fusion of registered images, an image stitching and fusion algorithm circuit based on a dynamic programming algorithm to search for seam lines was proposed. Comprehensive experimental results and a theoretical analysis based on Cyclone IV FPGA devices show that, with a clock frequency of 100 MHz, the proposed circuit takes about 7.04 ms to carry out the fusion processing of two 486 × 643 images, and the corresponding frame rate is approximately 142 FPS, achieving a perfect real-time stitching effect and meeting the demand for real-time image processing. After a theoretical derivation and comparison with other similar works, its processing speed is better than four state-of-the-art implementations.
- Open Access
- 25 October 2021
- Published by MDPI AG in Electronics
- Vol. 10 (21) , 2600
A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors
Since memristor was found, it has shown great application potential in neuromorphic computing. Currently, most neural networks based on memristors deploy the special analog characteristics of memristor. However, owing to the limitation of manufacturing process, non-ideal characteristics such as non-linearity, asymmetry, and inconsistent device periodicity appear frequently and definitely, therefore, it is a challenge to employ memristor in a massive way. On the contrary, a binary neural network (BNN) requires its weights to be either +1 or −1, which can be mapped by digital memristors with high technical maturity. Upon this, a highly robust BNN inference accelerator with binary sigmoid activation function is proposed. In the accelerator, the inputs of each network layer are either +1 or 0, which can facilitate feature encoding and reduce the peripheral circuit complexity of memristor hardware. The proposed two-column reference memristor structure together with current controlled voltage source (CCVS) circuit not only solves the problem of mapping positive and negative weights on memristor array, but also eliminates the sneak current effect under the minimum conductance status. Being compared to the traditional differential pair structure of BNN, the proposed two-column reference scheme can reduce both the number of memristors and the latency to refresh the memristor array by nearly 50%. The influence of non-ideal factors of memristor array such as memristor array yield, memristor conductance fluctuation, and reading noise on the accuracy of BNN is investigated in detail based on a newly memristor circuit model with non-ideal characteristics. The experimental results demonstrate that when the array yield ≥ 5%, or the reading noise ≤ 0.25, a recognition accuracy greater than 97% on the MNIST data set is achieved.- 25 October 2021
- Published by MDPI AG in Electronics
- Vol. 10 (21) , 2600
Open AccessA Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors
Since memristor was found, it has shown great application potential in neuromorphic computing. Currently, most neural networks based on memristors deploy the special analog characteristics of memristor. However, owing to the limitation of manufacturing process, non-ideal characteristics such as non-linearity, asymmetry, and inconsistent device periodicity appear frequently and definitely, therefore, it is a challenge to employ memristor in a massive way. On the contrary, a binary neural network (BNN) requires its weights to be either +1 or −1, which can be mapped by digital memristors with high technical maturity. Upon this, a highly robust BNN inference accelerator with binary sigmoid activation function is proposed. In the accelerator, the inputs of each network layer are either +1 or 0, which can facilitate feature encoding and reduce the peripheral circuit complexity of memristor hardware. The proposed two-column reference memristor structure together with current controlled voltage source (CCVS) circuit not only solves the problem of mapping positive and negative weights on memristor array, but also eliminates the sneak current effect under the minimum conductance status. Being compared to the traditional differential pair structure of BNN, the proposed two-column reference scheme can reduce both the number of memristors and the latency to refresh the memristor array by nearly 50%. The influence of non-ideal factors of memristor array such as memristor array yield, memristor conductance fluctuation, and reading noise on the accuracy of BNN is investigated in detail based on a newly memristor circuit model with non-ideal characteristics. The experimental results demonstrate that when the array yield ≥ 5%, or the reading noise ≤ 0.25, a recognition accuracy greater than 97% on the MNIST data set is achieved.