Sung-Soo Min

This paper proposes a novel cascade voltage-control method for DC variable-speed synchronous generators with a diode rectifier. In order to emphasize the necessity of the proposed method, the light-load voltage fluctuation problem that affects the conventional control method is analyzed based on a simplified excitation system model. In this analysis, two operation modes of the diode-front-end rectifier are presented: the rectifier mode and the discharging mode. Between the two modes, integral windup in the discharging mode is considered to be the main cause of light-load DC voltage fluctuations in the conventional voltage-control method, and a range of parameters to avoid the discharging mode is designed considering the characteristics of DC variable-speed synchronous generators. However, because there are tradeoffs between the response time and stable operation in the conventional method, a cascade voltage-control method is proposed to improve the performance in both modes. In the proposed method, the voltage-control loop is divided into an inner and outer voltage-control loop. The inner loop indirectly controls the DC voltage with fast dynamics while the outer loop ensures stable and accurate operation. When applying the proposed method, no windup occurs in the discharging mode, eliminating the cause of light-load voltage fluctuations. The proposed cascade voltage-control method is verified through both a PSIM-based simulation and experimentally.

Active clamp forward (ACF) converters are being extensively applied to auxiliary power modules (APMs) in electric vehicles (EVs) to minimize the use of components and maximize efficiency. Existing ACF converter designs disregard the parasitic characteristics of the components and the leakage inductance of the transformer, resulting in design inaccuracies. This paper proposes a precise design method that considers the transformer impedance and parasitic characteristics of the components. Furthermore, the input–output relationship of the converter, stress on the switching components, and operational range are analyzed to introduce a design strategy that can minimize design errors. Moreover, this study implements a small-signal model and a controller design method based on the contrived model. The proposed design approach is validated through theoretical analysis, simulation comparison, and experimental verification, which includes the accuracy verification of the controller. This approach focuses on markedly reducing design errors, enhancing the precision of the ACF converter design, and further strengthening the reliability of converters for APM of an EV.

SiC MOSFETs are used in many power conversion applications because of their superior characteristics, such as fast switching speed, low on-resistance, and high operating temperature. In certain high-power systems, SiC MOSFETs are connected in parallel to enhance their current capacity and power efficiency. However, compared with Si-based devices, the current imbalance caused by the parasitic inductance difference becomes more severe when driving SiC MOSFETs in parallel, owing to the fast switching speed. Furthermore, the power loop inductance imbalance that occurs when constructing a half-bridge with parallel SiC MOSFETs has rarely been addressed in previous studies. In this study, a half-bridge switching power module based on parallel-connected SiC MOSFETs is proposed to solve the current imbalance through a symmetric structure of the gate and power loops. The effects of the magnitude and imbalance of the gate and power loop inductances in the half-bridge structure based on parallel-connected devices are also explained. A detailed printed circuit board layout of the proposed switching power module is provided, and the inductance symmetry is verified through simulations. A double-pulse test is conducted to verify the current-balancing capability of the proposed switching power module. In addition, an LLC resonant converter is designed using the proposed switching power module, and the power loss between parallel SiC MOSFETs is compared. The experimental results indicate the total power loss error between the parallel-connected SiC MOSFETs of the proposed power module is only 1.94%.

An LLC resonant converter should have high efficiency and power density. Further, it is important to reduce the volume and loss of the transformer, which provides insulation and voltage conversion between the input and output. When a planar core is used to achieve high power density, the magnitude of the parasitic components and the transformer loss considerably depend on the winding arrangement within the limited window area. Therefore, analyzing the various winding arrangements is necessary. To this end, an interleaved serpentine winding method that reduces the winding loss attributed to the high current by maximizing the window area of the planar core and has advantages of low parasitic capacitance and excellent assembly is proposed. The proposed winding method uses a Litz wire to reduce the DC copper loss, and it does not require additional space for the winding arrangement compared to that required by the U-type winding method. The capacitive energy distribution of the proposed winding method is compared with that of the existing U-type winding method to confirm the parasitic capacitance reduction effect of the proposed winding method. The formulae for calculating the effective capacitance of each winding method are derived for accurately estimating the parasitic capacitance. Finally, the effectiveness of the proposed analysis method and prototype are verified through finite element analysis simulation and experiments and it shows improvement of current waveforms and the overall efficiency increases about 0.5%.

Wide bandgap (WBG) power semiconductors can achieve high efficiency and power density due to their low on-resistance and fast switching speeds. However, the fast-switching speed induces voltage to the parasitic inductance in the circuit, causing a significant overshoot in the drain-source voltage of the devices and the ringing of the drain current due to resonance with the parasitic capacitance. Thus, minimizing parasitic inductance is necessary for driving WBG power semiconductors in a stable manner. This paper proposes a three-dimensional lattice structure that reduces parasitic inductance through horizontal and vertical magnetic flux cancellations within a printed circuit board (PCB). The relationship between the magnetic flux cancellation and the parasitic inductance is analyzed, and the magnetic flux cancellation in the proposed structure is described. In addition, a practical PCB layout design procedure based on the proposed structure is provided. Simulation results demonstrate a 55.8% reduction in parasitic inductance, and experimental results show reduced overshoot and ringing at the switching transient, resulting in a 26% reduction in switching loss. As a result, the proposed method can improve the efficiency and stability of WBG device-based power converters.

This paper applies a structural technique with uniform parallel switch characteristics in gates and power loops to minimize the ringing and current imbalance that occurs when a general discrete package (TO-247)-based power semiconductor device is operated in parallel. Also, this propose a heat sink integrated switching module with heat sink design flexibility and high power density. The developed heat dissipation-integrated switching module verifies the symmetry of the parasitic inductance of the parallel switch through Q3D by ansys and the validity of the structural technique of the parallel switch using the LLC resonant converter experiment operating at a rated capacity of 7.5 kW.

Among the wide-bandgap devices, gallium nitride high electron mobility transistors (GaN HEMTs) are contributing to the high power density technology of power conversion systems due to their excellent physical properties. In contrast, the driving voltage and threshold voltage are relatively low compared to conventional power semiconductor devices, so a reliable circuit design is required. In this paper, a parasitic inductance reduction design method for the stable driving of GaN HEMTs is proposed. To reduce parasitic inductance, we propose a vertical lattice loop structure having multiple loops, and this method can be applied regardless of the package type and shape of GaN HEMT. For the design of the proposed vertical lattice loop structure, the reference loop is defined to minimize leakage inductance and the identical loop is vertically stacked. The proposed structure is applied 6-layer PCB design example and verified by experimental results. Furthermore, the proposed design method is applied at the buck converter, and improved efficiency is verified from 600 kHz to 1MHz switching frequency.

Wide bandgap (WBG) power semiconductors are used in numerous power conversion applications because of their excellent switching characteristics. However, it is difficult to ensure short-circuit protection for WBG power semiconductors because of their shorter short-circuit withstand time. The fast-switching characteristics of WBG power semiconductors induces severe fluctuations in the drain-source voltage and drain current in switching transients, which results in the false triggering of the protection circuit. Therefore, the fast response speed and switching noise suppression are key requirements of the protection circuit for a WBG power semiconductor. To meet these requirements, an improved gate-voltage-driven desaturation protection circuit with a fast response speed and robust noise immunity is proposed in this study. The effect of switching noise on the proposed protection circuit is analyzed, and a detailed design procedure based on the analysis results is provided. The experimental results indicate that the protection delay of the proposed circuit is within 91 ns; additionally, the proposed circuit can survive switching noise during normal operation. Finally, the noise immunity analysis results are verified through experiments under various protection circuit parameter sets.