Giuk Kim

We present a ferroelectric nand (FeNAND) cell incorporating an engineered InGaZnO (IGZO) charge trap layer (CTL) within a metal-gate interlayer (G.IL)-oxide semiconductor (OS)–ferroelectric (FE)-channel interlayer (Ch.IL)-semiconductor (MISFIS) gate-stack for highly reliable 3-D integration. Conventional MIFIS-based FeNAND cells suffer from endurance degradation driven by oxygen vacancy ( ${V}_{\text {O}}\text {)}$ accumulation and severe memory window (MW) loss during retention caused by charge emission at the G.IL/FE interface. To address these limitations, a 2-nm-thick IGZO CTL is introduced, functioning simultaneously as: 1) an oxygen reservoir that suppresses ${V} _{\text {O}}$ -induced endurance failure and 2) an energy barrier that mitigates charge loss during retention. Furthermore, in situ ${N}_{{2}}$ doping is employed to precisely tailor the trap profile, yielding deep-level dominant traps at an ${N}_{{2}}$ flow rate of 2 sccm. The optimized MISFIS FeNAND cell achieves a wide MW of 9.4 V at an operation voltage below 17 V, stable triple-level cell (TLC) retention over ten years, and robust endurance exceeding 80k program (PGM)/erase (ERS) cycles. These results confirm that the IGZO CTL-based MISFIS architecture overcomes key reliability challenges of conventional FeNAND structures and represents a strong candidate for next-generation high-density 3-D FE memory technologies.

We investigate the impact of gate metal work function (Ф_M) engineering on the performance of Metal - Interlayer – Ferroelectric (FE) – Interlayer – Silicon (MIFIS) ferroelectric field effect transistors (FeFET). The gate injected trapped charge (Q_it’) plays a critical role in determining key device parameters such as the memory window (MW) and operating voltage (V_op), making Ф_M optimization a viable approach to enhance MIFIS FeFET performance. To evaluate this effect, we fabricated devices with Al (Ф_M = 4.1 eV), TiN (Ф_M = 4.7 eV), Pt (Ф_M = 5.35 eV) gate metals. A higher Ф_M reduces the valence band offset at the gate interlayer (G.IL), facilitating hole injection during program (PGM) operations. This results in a lower PGM V_op and a steeper incremental step pulse programming (ISPP) profile. Simulation results confirm that enhanced gate hole injection underpins the observed ISPP behavior. Additionally, high Ф_M gates reduce read after write delay (RAWD) and lower de-trap pulse amplitudes. Our findings establish gate Ф_M engineering as an effective strategy to improve MIFIS FeFET performance, particularly for low-voltage operation and disturbance mitigation.

The concept of negative capacitance (NC), originating from the intrinsic energy configuration of HZO ferroelectrics, has been predominantly utilized in logic transistors to achieve a steeper Id-Vg characteristic. Departing from these conventional approaches, we have developed an NC-NAND flash memory by integrating the NC phenomenon into the blocking oxide layer of conventional NAND flash memory. By leveraging the capacitance boosting effect of the NC-integrated blocking oxide (BO) layer, we can significantly enhance program (PGM) efficiency and lower the operating voltage of charge trap memory. In this work, we propose two combined approaches to improve the NC. First, we applied asymmetric tensile stress to the HZO layer through high-pressure annealing (HPA), thereby generating an internal electric field across the HZO layer. Additionally, we improved the polarization property of the HZO layer by employing a low-damage process during the deposition of the capping TiN electrode, minimizing interfacial damage to the HZO surface. Step-pulsed I-V measurement confirmed that the capacitance boosting effect of the NC blocking oxide with the low-damage process was improved by 16.7%, while the operating voltage was reduced by 1 V. Additionally, the NC-NAND flash memory with the low-damage process exhibited a significant higher ISPP slope characteristic.

The ferroelectric (FE) NAND flash, featuring metal-interlayer-FE-interlayer-silicon (MIFIS) gate stacks, leverages both charge trapping and polarization (△ P ) switching to achieve a broad memory window (MW) and low operation voltage. These remarkable advancements establish it as a viable contender for future NAND flash technologies. However, the read-after-write-delay (RAWD) problem during program/erase (PGM/ERS), caused by channel-injected interface trapped charges ( Q _it ) between the FE layer and the channel interlayer (Ch.IL), leading to short-term V _th variations, remains unexplored in MIFIS FE-NAND cells. This letter presents the first analysis of RAWD in FE-NAND cells, including the experimental optimization of a de-trap pulse that effectively eliminates Q _it whereas preserving both gate-injected interface trapped charges ( Q _it ') and △ P . Consequently, the FE-NAND cell exhibits a narrow MW of 3.45 V at a delay time ( t _Delay ) of 1 μs between PGM/ERS and read operations, expending to 7.40 V at a t _Delay of 1 s. This variation is attributed to the generation of Q _it and the subsequent de-trap process, affecting channel conductivity. To thoroughly address the RAWD, various pulse widths and amplitudes are experimentally explored immediately post-PGM/ERS to optimize the de-trap pulse for selective Q _it removal. Upon applying the optimized de-trap pulse, the stable wide MW (7.40 V) is consistently maintained regardless of t _Delay . This work is meaningful as it brings attention to previously unexplored issues in next-generation ferroelectric (FE) NAND cells and suggests practical operational solutions.

Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) FeFETs have significant potential for use in non-volatile memory applications. This is primarily due to their compatibility with CMOS technology and reliable switching characteristics. Previous studies have primarily concentrated on the endurance and memory window properties, while this study focuses on the short-term (<1 μ s) retention region of MFMIS FeFETs. Specifically, we examine the impact of the capacitance ratio of the ferroelectric capacitor (CFE) and the MOS capacitor (CDE) on short-term retention. Additionally, we conducted simulations to validate the experimental observations and investigate the interaction of the depolarization field with the charge trapping and polarization of the MFMIS structure. This study emphasizes the crucial role of controlling the CDE: CFE ratio in enhancing the short-term retention of MFMIS FeFETs. Its findings enhance our understanding of short-term retention mechanisms and provide a pathway for improving performance and functionality in non-volatile memory technology design.

Hafnia-based ferroelectrics (FEs) can be stabilized via careful engineering, both kinetically and thermodynamically. Especially, the fast cooling process has been regarded as an efficient approach for kinetically maximizing the phase transition to the orthorhombic ( o -) phase from the tetragonal ( t -) phase, which stabilizes thermodynamically during crystallization annealing. However, accurately controlling the cooling period for fast cooling procedures is challenging, resulting in unreliable and nonreproducible outcomes and interpretation. Thus, until now, comprehending its effects has mainly relied on modeling efforts in the field of material science. Here, for the first time, we experimentally validate the fast-cooling effect with Al:HfO $_{\text{2}}$ FEs, based on the novel equipment ensuring both reliability and reproducibility. In addition, it enabled us to investigate the impact of the fast cooling process on the phase, domain size, and interface quality of FEs through various electrical analyses. The fast cooling technique facilitates the transition from the t -phase to the desired o -phase, inducing significantly higher remanent polarization values of 2 $\textit{P}_{\textit{r}}$ (35.31 $\mu$ C/cm $^{\text{2}}\text{)}$ and improved subloop characteristics. In contrast, slow cooling (2 $\textit{P}_{\textit{r}}$ of 9.50 $\mu$ C/cm $^{\text{2}}\text{)}$ leads to poor subloop properties. Given that a fast cooling procedure is useful for stabilizing the FE o -phase in thin films, we believe that our reliable annealing procedure and significant experimental findings can provide a foundation for future studies in hafnia FE material and memory devices.

In this study, we investigated the impact of unstable and stable interface trap charges ( ${Q}_{\text {it}}\text {)}$ on ${P}_{\text {S}}$ switching in metal-ferroelectric–insulator-Si (MFIS) ferroelectric field-effect transistors (FeFETs), which vary with the thickness of the insulator. We also examine how these variations ultimately affect the various performance metrics of MFIS FeFETs. To achieve this, we varied the thickness of the insulator ( ${t}_{\text {IL}}\text {)}$ in MFIS FeFETs to 1.5, 2.0, and 2.5 nm, thereby controlling the amount of ${Q}_{\text {it}}$ injected from the channel into the ferroelectric (FE)/insulator interface. As ${t}_{\text {IL}}$ decreases, the amount of ${Q}_{\text {it}}$ increases, which amplifies the electric field across the FE layer. As a result, ${P}_{\text {S}}$ switching enhances, and consequently, the MW characteristics of MFIS FeFETs improve. Furthermore, to analyze this in detail, we employed ${P}_{\text {S}}$ – ${Q}_{\text {it}}$ measurements on MFIS FeFETs to simultaneously extract unstable and stable ${Q}_{\text {it}}$ as well as ${P}_{\text {S}}$ and MW. The results show that as ${t}_{\text {IL}}$ increases to 1.5, 2.0, and 2.5 nm, ${Q}_{\text {it}}$ during program/erase (PGM/ERS) operations decreases to 100%, 61%, and 54%, respectively. This leads to a corresponding decrease in ${P}_{\text {S}}$ to 100%, 59%, and 52%. Additionally, after sufficient delay following the PGM/ERS operations, we observe that the proportion stable ${Q}_{\text {it}}$ compared to ${P}_{\text {S}}$ is 91%, regardless to ${t}_{\text {IL}}$ and the remaining 9% of ${P}_{\text {S}}$ contributes to the MW property. Consequently, as ${t}_{\text {IL}}$ increases to 1.5, 2.0, and 2.5 nm, the net charge decreases to 100%, 61%, and 54%, resulting in MW values of 1.85, 1.05, and 0.85 V, respectively. Finally, we analyzed the impact of ${Q}_{\text {it}}$ generation as a function of ${t}_{\text {IL}}$ on the variability and endurance characteristics of MFIS FeFETs.

This study employs analytical simulation to illustrate the beneficial correlation between interface trapped charge and spontaneous polarization ( P_S ) switching behavior in the MIFIS gate stack. We found that there is a positive interaction between charge trapping and polarization switching, comprising three sequential processes. (i) In the process of program (erase) operation, electrons (holes) are introduced from the gate metal and are trapped at the interface between the gate interlayer (gate-IL) and the ferroelectric layer. (ii) The trapped charge amplifies the electric field across the ferroelectric (FE) layer, subsequently enhancing PS. (iii) The increase in PS intensified the induced field on the gate-IL which boosts the charge injection. The three processes are reiterated as previously mentioned. The results indicate that the significant memory window (MW) observed in MIFIS ferroelectric field-effect transistor (FeFET) is a consequence of the combined effect of trapped charges and polarization switching charges, rather than separate contributions. Lastly, with the calibrated simulation model, we provide strategies to improve the device performance in terms of MW and operation speed. The experimental findings and analytic comprehension in this work provide a foundation for future researches on FeFET.