Kairui Tian

The emerging Massive Communication (MC) highlights the need for efficient short-length error-correction coding schemes with effective decoders. Classical Reed-Muller (RM) codes combined with the recently developed Recursive Projection-Aggregation (RPA) decoder present a promising solution, as the RPA decoder demonstrates near Maximum Likelihood (ML) performance and supports highly parallel implementation. To address the speed and flexibility requirements of Cloud Radio Access Networks (C-RANs) across various MC applications, this paper proposes a fast and scalable RPA decoder on Graphics Processing Units (GPUs). By leveraging a thread-per-projection mapping strategy, we develop an optimized thread block architecture for the RPA decoding of second-order RM codes, which can be easily extended to construct a multi-dimensional block array for decoding higher-order RM codes. Additionally, we introduce a stationary projection pruning technique that seamlessly adapts the RPA decoder kernel to simplified variants, facilitating flexible trade-offs between error-correction performance and implementation complexity. Experimental results show that the pruned RPA decoder kernel on the NVIDIA A100 GPU achieves throughputs of 1.69 Gbps and 1.33 Gbps for the RM (6, 2) and RM (7, 2) codes, respectively, delivering speedups of 2.95× and 3.69× compared to a state-of-the-art software-based Successive Cancellation List (SCL) decoder.

The newly developed automorphism ensemble decoder (AED) leverages the rich automorphisms of Reed–Muller (RM) codes to achieve near maximum likelihood (ML) performance at short code lengths. However, the performance gain of AED comes at the cost of high complexity, as the ensemble size required for near ML decoding grows exponentially with the code length. In this work, we address this complexity issue by focusing on the factor graph permutation group (FGPG), a subgroup of the full automorphism group of RM codes, to generate permutations for AED. We propose a uniform partitioning of FGPG based on the affine bijection permutation matrices of automorphisms, where each subgroup of FGPG exhibits permutation invariance (PI) in a Plotkin construction-based information set partitioning for RM codes. Furthermore, from the perspective of polar codes, we exploit the PI property to prove a subcode estimate convergence (SEC) phenomenon in the AED that utilizes successive cancellation (SC) or SC list (SCL) constituent decoders. Observing that strong SEC correlates with low noise levels, where the full decoding capacity of AED is often unnecessary, we perform path pruning to reduce the decoding complexity without compromising the performance. Our proposed SEC-aided path pruning allows only a subset of constituent decoders to continue decoding when the intensity of SEC exceeds a preset threshold during decoding. Numerical results demonstrate that, for the FGPG-based AED of various short RM codes, the proposed SEC-aided path pruning technique incurs negligible performance degradation, while achieving a complexity reduction of up to 67.6%.

Automorphism ensemble decoding (AED) is a highly parallel approach that enables decoding of polar and Reed-Muller (RM) codes with automorphisms, offering a practical solution with near-maximum likelihood (ML) performance and manageable computational complexity. To meet the growing demands for high throughput and low latency in cloud and virtual random access networks, this paper presents a graphics processing unit (GPU)-based AED architecture for polar and RM codes, utilizing low-complexity successive cancellation (SC) and small list SC (SCL) decoders as the constituent of AED. The proposed architecture exploits the inherent parallelism of AED to optimize decoding tasks on the GPU, significantly enhancing throughput by efficiently harnessing the extensive parallel processing capabilities of the GPU. Additionally, improved thread mapping and data management techniques markedly reduce latency for automorphism ensemble SC (Aut-SC) decoding, while a low-latency sorting mechanism further accelerates automorphism ensemble SCL (Aut-SCL) decoding. Experimental results on an NVIDIA RTX 4090 demonstrate that the proposed Aut-SC decoder, with an ensemble size of 8, achieves a throughput exceeding 17 Gbps. Compared to the state-of-the-art softwarebased SCL decoders, the proposed GPU-based Aut-SC and Aut-SCL architectures outperform existing solutions by factors of up to 28× and 10×, respectively, in normalized throughput while maintaining the same or even superior error correction performance.

The Multiple Symbol Detection (MSD) algorithm can effectively lower the demodulation threshold in Frequency Modulation (FM) technology, which is widely used in aircraft wireless communications due to its insensitivity to large Doppler shifts. However, the high computational complexity of the MSD algorithm leads to considerable hardware resource overhead. In this paper, we propose a novel MSD architecture based on hybrid stochastic computing (SC), which allows for accurate signal detection while maintaining low hardware complexity. Given that the correlation calculation dominates the computational load in the MSD algorithm, we develop an SC-based, low-complexity unit to perform complex correlation operations using simple hardware circuits, significantly reducing the hardware overhead. Particularly, we integrate a flexible and scalable stochastic adder in the SC-based correlation calculation, which incorporates an adjustable scaling factor to enable high distinguishability in all possible correlation results. Additionally, for the symbol decision process of the MSD algorithm, we design a binary computing-based pipeline architecture to execute the computing process serially, which leverages the inherent low update rate of SC-based correlation results to further reduce the overall resource overhead. Experimental results show that, compared to an 8-bit quantization MSD implementation, our proposed hybrid SC-based MSD architecture achieves a comparable bit error rate while reducing the hardware resources to 69%, 45%, and 36% of those required for the three-, five-, and seven-symbol MSD algorithms, respectively.

Multiple Phase Shift Keying (MPSK) and Multiple Amplitude Phase Shift Keying (MAPSK) represent widely adopted modulation techniques in satellite communications, primarily due to their characteristic of low peak-to-average ratio. However, the rapid mobility of satellites induces substantial Doppler frequency shifts, which poses formidable challenges for carrier synchronization in coherent receivers. Consequently, this paper presents a carrier synchronization algorithm based on the Attached SYNC Marker (ASM). The proposed approach leverages the ASM embedded within the data frame structure as prior knowledge to estimate the carrier error and correct the local oscillator. Considering that the Doppler frequency offset may significantly exceed the estimated range, the Low Density Parity Check (LDPC) code syndrome check is employed to facilitate the determination of Doppler frequency. The experimental results confirm that the frequency estimation error is a few hundred hertz, the phase estimation error is around 0.1, and the maximum bit error rate (BER) performance loss is approximately 0.5dB. These results substantiate the effectiveness of proposed method in carrier synchronization for MPSK and MAPSK signals.

For polar codes, the statistical breakdown of belief propagation (BP) decoding errors is firstly proposed by Sun et al. The errors are classified into three categories: unconverged errors, false converged errors and oscillation errors, which are corrected by three different post-processing methods. As for the BP List (BPL) decoding, we discover that one type of error can be transformed to another type by different factor graphs in the failed BP decoding. Besides, false converged error is usually easier to be detected and modified. Therefore, we only target false converged error to detect and correct. In this work, we propose a two-level detection rule for false converged errors and its corresponding post-processing algorithm to modify these errors in order to improve the performance of the BPL decoding. Numerical results show that the error-correction performance of the proposed decoder is more than 0.85dB better than that of the permuted BPL (PBPL) decoder with slight extra computation complexity at the frame error rate (FER) of 10-5 for 5G (1024,512) polar code.