Oliver Griebel

In channel coding, reducing power consumption and improving energy efficiency are major challenges in sliding window decoding (SWD) architectures for spatially coupled low-density parity-check (SC-LDPC) codes. In contrast to the well-elaborated literature on energy-efficient decoder implementations of classical LDPC block codes (LDPC-BCs), there is little research on the aforementioned challenges for SC-LDPC codes. Thus, in this paper, we investigate a novel approach for energy-efficient implementation of very high-throughput SWD for SC-LDPC codes. First, our approach proposes an analogy to state-of-the-art iteration control techniques for LDPC-BC decoders, by dynamically adapting the window size for the decoding of SC-LDPC codes. For this purpose, we derive new algorithms that sequentially activate and/or deactivate the processors inside the window, without loss in error correction performance. Second, we propose an architecture for very high-throughput decoder implementations. Furthermore, to meet the high throughput requirements and improve energy efficiency, we revisit the window-size adaption criteria and slightly relax the derived algorithms in terms of error correction capability. Implementation results of the new revisited full-adaptive decoder in a 12 nm technology show that, at a negligible loss in error correction performance, the proposed adaptive SWD approach improves the energy efficiency by a factor of 1.4 to 3.4 compared to the state-of-the-art in the 4 dB to 7 dB signal-to-noise-ratio (SNR) range. This improvement is further increased up to a factor of 6.5 at higher SNRs.

In Message Passing (MP) decoding of Low-Density Parity Check (LDPC) codes, extrinsic information is exchanged between Check Nodes (CNs) and Variable Nodes (VNs). In a practical implementation, this information exchange is limited by quantization using only a small number of bits. In recent investigations, a novel class of Finite Alphabet Message Passing (FA-MP) decoders are designed to maximize the Mutual Information (MI) using only a small number of bits per message (e.g., 3 or 4 bits) with a communication performance close to high-precision Belief Propagation (BP) decoding. In contrast to the conventional BP decoder, operations are given as discrete-input discrete-output mappings which can be described by multidimensional LUTs (mLUTs). A common approach to avoid exponential increases in the size of mLUTs with the node degree is given by the sequential LUT (sLUT) design approach, i.e., by using a sequence of two-dimensional Lookup-Tables (LUTs) for the design, leading to a slight performance degradation. Recently, approaches such as Reconstruction-Computation-Quantization (RCQ) and Mutual Information-Maximizing Quantized Belief Propagation (MIM-QBP) have been proposed to avoid the complexity drawback of using mLUTs by using pre-designed functions that require calculations over a computational domain. It has been shown that these calculations are able to represent the mLUT mapping exactly by executing computations with infinite precision over real numbers. Based on the framework of MIM-QBP and RCQ, the Minimum-Integer Computation (MIC) decoder design generates low-bit integer computations that are derived from the Log-Likelihood Ratio (LLR) separation property of the information maximizing quantizer to replace the mLUT mappings either exactly or approximately. We derive a novel criterion for the bit resolution that is required to represent the mLUT mappings exactly. Furthermore, we show that our MIC decoder has exactly the communication performance of the corresponding mLUT decoder, but with much lower implementation complexity. We also perform an objective comparison between the state-of-the-art Min-Sum (MS) and the FA-MP decoder implementations for throughput towards 1 Tb/s in a state-of-the-art 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology. Furthermore, we demonstrate that our new MIC decoder implementation outperforms previous FA-MP decoders and MS decoders in terms of reduced routing complexity, area efficiency and energy efficiency.

Carrier synchronization is a crucial part of any wireless receiver, which is required due to frequency and phase offset. In case of transmission in a Time Division Multiple Access system the carrier synchronization has to be carried out for every burst separately. The DVB-RCS2 standard specifies a large variety of reference burst types with very limited known symbols. For each of these types a thorough exploration of different synchronization algorithms is required to find a trade-off between a good communication performance at very low Signal to Noise Ratio (SNR) and an efficient hardware implementation. A state-of-the-art algorithm for carrier synchronization is based on the so called Fast Fourier Transformation (FFT). An inherit limitation for the precision of frequency estimation is given by the FFT point size. To counteract this limitation, the FFT point size must be increased. In this paper we extensively compare two possible interpolation techniques for FFT results in three FFT-based carrier synchronization methods. These are applied to various reference burst types specified in the DVB-RCS2 standard. The trade-offs of these combinations are identified with a special focus on hardware implementation efficiency. Furthermore, we present a flexible IP core which can process the three synchronization methods in an efficient way and analyze its implementation complexity and throughput on a Xilinx Kintex FPGA.