Ahmed Gomaa Radwan

The design of an efficient Pseudo Random Number Generator (PRNG) with good randomness properties is an important research topic because it is a core component in many applications. Based on an extensive study of most PRNGs in the past few decades, this paper categorizes six distinct design scenarios under two primary groups: non-chaotic and chaotic generators. The non-chaotic group comprises Linear Feedback Shift Registers (LFSR) with S-Boxes, primitive roots, and elliptic curves, whereas the chaotic group encompasses discrete, continuous, and fractional-order chaotic generators. This paper delves into the related scientific summaries, equations, flowcharts, and designs with necessary recommendations for each PRNG scenario. Even though the focus is on the basic design characteristics that provide simple, functional and secure PRNGs, it is possible to enhance those designs for additional features and improved efficiency. Simulation outcomes and system key configurations, which produce long random sequences, are also presented and evaluated using leading criteria. The evaluation criteria include the National Institute of Standards and Technology (NIST) SP-800-22 test suite, TestU01 randomness tests, histogram, entropy, autocorrelation, and cross-correlation. Furthermore, key space, key sensitivity, and bit rate indicate that all designed examples meet international standards with high quality. The presented PRNGs are compared and integrated into an image encryption system. Although each PRNG design scenario can have a different key space, simple designs with fixed-length system keys are chosen for the sake of proper comparisons. Statistical and security assessments of the encryption system demonstrate that the PRNGs are cryptographically secure.

Secret image sharing (SIS) conveys a secret image to mutually suspicious receivers by sending meaningless shares to the participants, and all shares must be present to recover the secret. This paper proposes and compares three systems for secret sharing, where a visual cryptography system is designed with a fast recovery scheme as the backbone for all systems. Then, an SIS system is introduced for sharing any type of image, where it improves security using the Lorenz chaotic system as the source of randomness and the generalized Arnold transform as a permutation module. The second SIS system further enhances security and robustness by utilizing SHA-256 and RSA cryptosystem. The presented architectures are implemented on a field programmable gate array (FPGA) to enhance computational efficiency and facilitate real-time processing. Detailed experimental results and comparisons between the software and hardware realizations are presented. Security analysis and comparisons with related literature are also introduced with good results, including statistical tests, differential attack measures, robustness tests against noise and crop attacks, key sensitivity tests, and performance analysis.

The frequency response of the fractional-order power-law filter can be approximated by different techniques, which eventually affect the expected performance. Fractional-order control systems introduce many benefits for applications like compensators to achieve robust frequency and additional degrees of freedom in the tuning process. This paper is a comparative study of five of these approximation techniques. The comparison focuses on their magnitude error, phase error, and implementation complexity. The techniques under study are the Carlson, continued fraction expansion (CFE), Padé, Charef, and MATLAB curve-fitting tool approximations. Based on this comparison, the recommended approximation techniques are the curve-fitting MATLAB tool and the continued fraction expansion (CFE). As an application, a low-pass power-law filter is realized on a field-programmable analog array (FPAA) using two techniques, namely the curve-fitting tool and the CFE. The experiment aligns with and validates the numerical results.

Hardware accelerators outperform CPUs in terms of performance by parallelizing the algorithm architecture and using the device’s programmable resources. FPGA is a type of hardware accelerator that excels not only in performance but also in energy efficiency. So, it provides a suitable platform for implementing complicated fractional-order systems. This paper proposes a novel phase-based optimization method to implement fractional operators using FIR and IIR filters. We also compare five fractional operator implementation methods on FPGA regarding resource utilization, execution time, power, and accuracy. These methods and the proposed one are evaluated in terms of power consumption, delay, and resources to assist the designer in determining the most suitable implementation method for the given application. The proposed method has a lower phase error of $14.7\%$ in the case of derivative operation and a lower phase error of $18.83\%$ in the case of integration compared to the literature. In addition, the proposed methods decreased the consumed power and area by more than three times compared to the fixed-window GL fractional operator. The proposed approach implements Heaviside’s inductor-terminated lossy line. In addition, it is employed as an edge detection kernel to demonstrate its effectiveness in image processing applications.