Qingfeng Zhang

After analyzing the causes and propagation paths of current leakage in conventional bidirectional amplifiers, this article proposes a novel bidirectional amplifier architecture to address this critical leakage issue. As the core anti-leakage design, cross-coupled capacitors are integrated to precisely suppress power leakage between the two differential paths. Furthermore, the collaborative design of the amplification unit’s optimal noise source impedance and load impedance significantly enhances the amplifier’s output efficiency and noise performance. To validate the proposed architecture, a prototype is fabricated using a commercial 55-nm SOI CMOS process for K/Ka-band satellite communication (SATCOM) applications, with a core area of $0.22~\text {mm}^{2}$ . Experimental results confirm that the amplifier achieves superior performance in both LNA and PA modes, fully verifying the feasibility and superiority of the proposed architecture. In LNA mode, it delivers a peak gain of 19.2 dB (18.5–20.5 GHz, 2.0-GHz 3-dB gain bandwidth), a minimum noise figure (NF) of 3.5 dB, and an input 1-dB compression point ( $IP_{1dB}$ ) ranging from −11.5 to −9.5 dBm. In PA mode, continuous-wave (CW) measurements demonstrate a peak gain of 18.4 dB (23.9–28.4 GHz, 4.5-GHz 3-dB gain bandwidth), a satu-rated output power ( $P_{sat}$ ) of 17.0 dBm, and a peak power-added efficiency (PAE) of 33.1% at 28 GHz. For 28-GHz modulated signals (100 MSym/s 64-QAM, 7.1-dB peak-to-average power ratio), it achieves an average output power ( $P_{avg}$ ) of 9.31 dBm, an adjacent channel leakage ratio (ACLR) of −31.4 dBc, and an error vector magnitude (EVM) of −26.4 dB.

This paper presents a generalized multi-granularity design of Millimeter-wave (mmWave) and terahertz (THz) on-chip antennas based on improved reinforcement learning (RL). The proposed framework takes the advantages of the modeling strategy, enhanced RL, and multi-granularity method, enabling high-degree-of-freedom on-chip antenna design with low-dimensional modeling parameters. Firstly, a parametric modeling strategy is introduced to achieve a pixelation-like design effect but circumventing high data quality and quantity requirements typically associated with conventional pixel-based methods. Secondly, the enhanced RL uses a Maximum Entropy Actor-Critic (MEAC) algorithm to improve convergence speed, robustness, and efficiency. Thirdly, field theory analysis is incorporated to decompose the optimization process into coarse and fine granularities, effectively minimizing redundant modeling in non-essential regions. This method is applied to D-band on-chip antenna design for the commercial1 65nm CMOS process and W-band for the commercial2 55nm CMOS process. The experimental results show that the D-band on-chip antenna achieves a relative bandwidth of 50.9% (100-177 GHz), a peak gain of 2.4 dBi, and a radiation efficiency of 62%, respectively, while the W-band achieves a relative bandwidth of 30.6% (69-95GHz), peak gain of 6.4dBi, and radiation efficiency of 72%. Compared with existing studies, the multi-granularity with enhanced reinforcement learning significantly improves bandwidth, gain, and radiation efficiency, with strong generalizability across different frequency bands and fabrication processes.

This article presents a wideband phased-array receiver (RX) front end featuring spatial in-band blocker suppression for 5G new radio (NR). A blocker-elimination (BE) circuit is positioned in shunt between two adjacent radio frequency (RF) channels’ output nodes to extract a blocker from RF channels and generate a corresponding canceling signal. As a result, the BE circuit enables the phased-array RX’s beam pattern to form a null aligned with the blocker’s incident angle, effectively suppressing interference. By integrating several BE circuits in a multi-channel RX system, it can simultaneously address multiple blockers arriving from different directions. A beam-tracking (BT) method is developed to detect unknown incident beams and estimate a blocker’s angle of arrival during desired signal transmission, leveraging three parallel phase-to-voltage conversion paths. Additionally, all building blockers in RF channels utilize wideband and high-linearity structures, providing multiple 5G-NR-band support and resilience against strong interference. The prototype phased-array RX is demonstrated in a 65-nm CMOS technology. Measurement results show that the chip successfully covers a frequency band of $22.4{\sim }30.7$ GHz with an input 1-dB compression point of ${-} 12.9{\sim } {-}12.1$ dBm. Root-mean-square (rms) phase and gain errors of each RX channel are less than 0.65° and 0.38 dB at $25.6{\sim }28.8$ GHz, respectively. Also, it achieves a tested error vector magnitude (EVM) of −34.19 dB for 400-MHz 256QAM modulation signal. Thanks to the proposed beam-pattern null-steering (BPNS) technique, a four-element phased-array RX system based on the RX chips achieves >30.2-dB spatial rejection against blockers at their beam angles in over-the-air (OTA) testing. OTA modulation signal measurements further demonstrate 3.3–6.9-dB EVM improvement across varying incident angles and power levels of an in-band blocker.

This letter proposes a hybrid topology optimization paradigm grounded in physical constraints, introducing a novel approach to electromagnetic (EM) structure design. The methodology simultaneously broadens the design space while compressing the search domain, effectively reducing dependence on a priori data. Central to the framework is the integration of reinforcement learning (RL) for dynamic constraint generation, synergistically combined with swarm intelligence algorithms for performance optimization. To validate the proposed approach, an input matching network for a low-noise amplifier (LNA) was designed and fabricated using a commercial GaAs process. The experimental results demonstrate that the LNA achieves a bandwidth of up to 5 GHz, a noise figure (NF) below 0.72dB, and a peak gain of 22.32 dB. Validated across multiple fabricated prototypes, the close agreement between simulation and measurement underscores the robustness and effectiveness of the proposed framework in achieving high-performance circuit design.

This article presents a physics-enhanced equivalent circuit model for high-frequency interconnections integrating ball grid arrays (BGAs) with redistribution layers (RDLs), fabricated using wide-ground coplanar waveguide (CPW) structures. Moving beyond existing models proficient in characterization of basic parameters, the core innovation lies in the establishing an equivalent circuit model that enables quantifiable calculation and early prediction of eddy current inductance. In addition, a refined method for accurately modeling the inductance within BGA interconnects is proposed. Based on this model, the scaling laws governing inductance parameters with respect to BGA pitch and the effects of varying numbers of ground bumps are also discussed. The proposed model demonstrates predictive accuracy above 92% for transmission characteristics across from 0.1 to 40GHz. Systematic validation using 15 distinct physical samples, covering diverse BGA and RDL configurations, confirms an error below 8% empirical fitting with measured data. This modeling tool significantly enhances design efficiency and reliability for millimeter-wave 3-D packaging and integration systems by providing fast and accurate simulation of critical interconnection performance.

This article presents a 22–31-GHz high-gain power amplifier (PA) with a stability–efficiency–reliability-enhanced serial–parallel current-reuse technique for 5G communications. The existing current-reuse techniques basically rely on the stacked coupling approach, which will have a risk of generating negative output impedance, resulting in potential instability and oscillation of the amplifier. Second, considering efficiency and reliability, another major problem is that they are inapplicable to power stage design, especially multiway high power. To address these issues, a novel single-level uncoupled serial–parallel current-reuse technique is proposed and applied to power stage for the first time. With this technique, the dc path of the power stage is equivalent to multiple common-emitter (CE) amplifiers in cascaded sharing the same current, and the final consumed total current is small instead of the sum of the individual ways, which can significantly alleviate the pressure on current intensity requirements, thereby enhancing the reliability, while the RF path is multiple CE amplifiers in parallel rendering both higher efficiency and stronger stability. Furthermore, a self-cancellation-based AM–PM distortion compensation technique is adopted to attain high linearity without sacrificing performance or introducing dramatic design complexity. The proposed PA with both techniques is demonstrated in a 0.13- $\mu$ m SiGe BiCMOS technology with a chip area including PADs of 0.56 mm $^{{2}}$ . It exhibits a measured peak gain of 31.9 dB with 3-dB bandwidth of 22.7–30.7 GHz. At such a high power gain, the PA is still unconditionally stable over all measured frequencies. Besides, the PA achieves a 16.2-dBm saturated output power ( ${P}_{{\text{sat}}}$ ), a 13.9-dBm output 1-dB compression point power (OP $_{{\text{1dB}}}$ ), and a 20.5% peak PAE. Without applying any predistortion, the prototype realizes a measured AM–PM distortion till OP $_{{\text{1dB}}}$ point of ${<}1^{\circ}$ and gain expansion in the linear region of ${<}0.3$ dB at 28 GHz. Modulated signal measurements are also performed at 28 GHz with 2.4-and 3.2-Gb/s symbol rates. The PA achieves 9.3-dBm average output power with $-$ 32.9-dBc adjacent channel leakage ratio (ACLR) and $-$ 24.1-dB error vector magnitude (EVM).

A variable gain amplifier (VGA) featuring wide bandwidth and low phase variation is presented for the new generation phased arrays supporting multiple-frequency bands simultaneously. In this article, the mechanism of phase variation in common-source (CS) CMOS amplifier cell is investigated in detail. As revealed by this analysis, the parasitic capacitor C $_{\text{gd}}$ and the magnetic coupling among inductors as well as parasitic capacitors in layout inducing by interconnection lines are some of the key factors that generate feedforward signal, which leads to the phase variation. The other is the inconstant input and output admittance that result in phase deviation over a wideband region. To achieve low phase variation over broadband for CMOS CS VGA, an innovative phase compensation method based on feedforward signal suppression (FSS) and impedance-invariant techniques is proposed. Specifically, the active cross-coupling neutralization topology is employed to suppress the feedforward signal generated by C $_{\text{\rm gd}}$ . Meanwhile, an isolation enhancement layout approach aiming at mitigating the inductive coupling and parasitic capacitors in layout is proposed. Besides, a control circuit based on the impedance-invariant technique is developed to minimize the impedance variation. As a result, a low phase variation VGA with broadband phase compensation is achieved. The measured gain control range is 23 dB, with a 3-dB bandwidth of 20–43 GHz and a peak gain of 15 dB. The measured phase variation is $<$ 2 $^{\circ}$ in 18–36 GHz and $<$ 6 $^{\circ}$ across 18–45 GHz. The noise figure and input-referred P $_{\text{1\,dB}}$ are 5.5 dB and $-$ 18 dBm in the maximum gain state, respectively. The measurement also shows the proposed VGA has good robustness against the variation of supply and temperature. The VGA consumes 30.8 mW from a 1.1-V voltage supply. The chip is fabricated in a standard 65-nm CMOS process and the core area is 0.34 mm $^{\text{2}}$ .

This letter investigates the mechanism of the phase characteristics versus frequency of the conventional and modified switched T-type attenuator cells in detail. According to the analysis, the optimal phase compensation interval for different topologies is revealed for the first time, which has important guiding significance for the design of ultralow phase error digital step attenuator (DSA) operating in different frequency bands. Furthermore, to verify the correctness and validity of the analysis, a $W$ -band 3-bit DSA was implemented in a standard 65-nm CMOS process. It achieves a measured dynamic attenuation range of 7-with 1-dB tuning step. With the help of the parallel-type capacitive phase compensation technique, the DSA exhibits a measured root-mean-square (rms) phase error of 1.1 $^{\circ}$ at 90.5 GHz and phase fluctuation of only 1.6 $^{\circ}$ across 85–105 GHz. Besides, the tested rms amplitude error is less than 0.6 dB. The core chip area of the designed DSA is 0.082 mm $^{2}$ . To the best of our knowledge, the effectiveness of parallel-type phase compensation technique based on switched T-type is first verified in $W$ -band.