Mookyoung Yoo

Conventional auto-zeroing (AZ) techniques suffered from drawbacks such as feedback stability issues caused by series capacitors in the signal path or increased current consumption due to the use of auxiliary amplifiers. The current-adjusting auto-zeroing (CAAZ) technique, which employs a simple structure that samples offset by adjusting the bias currents, was recently reported. This brief presents a low-offset operational amplifier employing a multipath ping-pong CAAZ stabilization technique. By leveraging the advantages of the previously reported CAAZ technique, this amplifier employs a ping-pong structure to enable continuous operation, while a multipath architecture consisting of high- and low-frequency paths ensures both wide bandwidth and enhanced offset performance. The amplifier is fabricated in a 0.18-μm CMOS process, consumes 196.9 μA from a 1.8 V supply, and achieves a unity-gain bandwidth of 5.01 MHz. It occupies 0.59 mm² and achieves an input-referred offset of 3.2 μV with a standard deviation of 3.8 μV.

This paper presents an implantable cardiovascular biopotential acquisition and stimulation circuit with body-channel (BC) data communication and power transfer capabilities for a transcatheter leadless pacemaker. The power and size requirements of leadless pacemakers, specifically for implantable electronics and minimally-invasive transcatheter delivery, are highly challenging. To reduce size, electrocardiogram (ECG) sensing, pacing, timing and control logic, and body- coupled wireless transceivers are integrated into a single chip. The ECG sensing channel is designed using a current-reused current-feedback instrumentation amplifier to reduce power consumption. The pacing circuit is implemented using a switched-capacitor stimulator with passive discharge for high stimulation efficiency. The pacemaker utilizes BC communication instead of RF communication to achieve low power consumption. The measured input-referred noise of the sensing channel is 3.69 μV_RMS, and the power consumption ranges from 4.5 to 19.4 μW. The downlink and uplink speeds of BC communication are 10 Mbps and 16 kbps, respectively. The internal rechargeable battery is properly charged when a 600 mV_PP, 20 MHz input signal is applied. The leadless pacemaker prototype is implemented with a small size of 5.89 mm and 26.5 mm in diameter and length, respectively. The performance of the leadless pacemaker prototype is evaluated through in vivo experiments using swine.

Physically unclonable function (PUF) generates a unique fingerprint or root of trust using the inherent randomness introduced during manufacturing. PUF outputs requires to be unique, random, robust, and unclonable. Dynamic random access memory (DRAM)-based PUFs are attractive due to their high density and randomness, achieved by controlling critical timings parameters, including tRCD, tRP, and tREF. Traditional DRAM PUFs use a single word-line (WL) to select individual cells connected to a bit-line (BL), generating random outputs through “absolute" mismatches in properties such as cell capacitance, leakage current, and charge redistribution timings. In this brief, we present a novel twin-cell DRAM PUF that employs “differential" mismatches between activated cells. Dual WLs in this design activated both twin-cells connected to the BL and bit-line bar (BLb). Leakage currents through the access transistors discharged the precharged cells, and the residual charges in the cell capacitances were redistributed to the BL capacitances following the discharge period. The sense amplifier amplified the relative mismatches between the twin-cells to generate the PUF output. The PUF was fabricated using a 28 nm complementary metal oxide semiconductor (CMOS) process. It operates at a nominal voltage of 1 V. It demonstrated 49.5% uniformity and 98.51% reliability under nominal voltage and temperature. The inter-chip Hamming distance (HD) was 45.91%, while the inter-WL HD and inter-PUF HD were 50.19% and 49.98%, respectively.

This study describes the design and development of a low-noise, process variation-tolerant potentiostat readout integrated circuit optimized for electrochemical sensors in biomedical applications. Accurate and fast detection by electrical signals, particularly for pathogenic viruses, is critical in the biomedical field. Therefore, design criteria for bio-signal sensing architectures emphasize high precision and low noise to ensure high reliability. The proposed potentiostat readout circuit integrates key components, such as a control amplifier (CA), transimpedance amplifier (TIA), 12-bit R-2R digital-to-analog converter (DAC), 12-bit SAR analog-to-digital converter (ADC), relaxation oscillator, clock divider, current/voltage reference, and serial peripheral interface. The chopping technique is adopted to mitigate the 1/f noise. The low-frequency noise is substantially reduced by implementing chopper stabilization in the CA and TIA. High precision DACs are required because various waveforms, including DC, triangular, and ramp functions, are utilized for electrochemical measurement. In this design, dynamic element matching is applied to DACs with high precision. This approach can reduce the intrinsic mismatch in the R-2R DAC, thereby improving the offset error and spurious free dynamic range from -1.4 LSB and 74 dB to -0.5 LSB and 79 dB, respectively. The readout circuit was fabricated using a standard 180 nm CMOS process and can measure sensor currents in the range of ±20 μA, achieving a linearity performance of 0.9998. The input-referred noise, as measured, is 6.65 pA _RMS in the frequency range of 0.5 to 400 Hz, and the total current consumption of the circuit is 339.6 μA at a supply voltage of 3.3 V.

A low noise operational amplifier is the key building block of the high precision sensor interface circuit. The conventional continuous-time operational amplifiers suffer from the low frequency noise components, and the multipath amplifiers are good solution to achieve both the low noise and wide bandwidth. This paper presents a low noise multipath chopper-stabilized operational amplifier with dual-path dual-chopper fill-in technique. The low-frequency path of the multipath amplifier is implemented using two dual-path chopper amplifiers. The noise correlation between the dual path chopper amplifiers can reduce the input referred noise level. The dual chopper amplifiers are driven by two quadrature chopper clocks. The glitch-free durations of the chopper amplifier outputs are combined using fill-in technique to reduce the unwanted switching artifacts including glitches and intermodulation distortions (IMDs). The circuit was fabricated using a 180 nm complementary metal-oxide-semiconductor (CMOS) process and draws 46.5 μA at a supply voltage of 1.8V. The input referred noise and input-referred offset are 6.42 nV/√Hz and 10.5 μV, respectively. The gain-bandwidth product is 874 kHz. The power supply rejection ratios (PSRR+ and PSRR-) and common mode rejection ratio (CMRR) are 118 dB, 111 dB and 90 dB, respectively. The chopper clock is 19 kHz. The IMD tones with 75 kHz is input are below -61 dB.

Resistive bridge sensors are used in many application areas to measure changes in physical parameters. To amplify the resistive changes from sensing elements with high precision, various offset contributors in the resistive bridge and amplifiers should be minimized. This study proposes a low-noise resistive bridge sensor analog front-end (AFE) using a chopper-stabilized multipath current feedback instrumentation amplifier (CFIA) and an automatic offset cancellation loop. The proposed circuit exploits a multipath chopper-stabilized architecture for obtaining low noise performance and wide bandwidth characteristics. This circuit can minimize the offsets in the bridge and the high frequency and low frequency amplifiers, while achieving high precision resistive signal acquisition. The high frequency path of the multipath amplifier uses the CFIA topology with class-AB output stage. The offset in the high frequency path is stabilized by the low frequency path amplifier with a high gain and low noise chopper amplifier. The up-modulated offset in the low frequency chopper amplifier path is reduced by the AC-coupled ripple reduction loop (RRL). An automatic offset calibration loop (AOCL) circuit was designed to calibrate the offset due to the bridge mismatch. The AOCL reduces the bridge offset using a successive approximation register (SAR)-based binary-search algorithm. The gain of the proposed circuit is adjustable from 15.56 dB to 44.14 dB. The AFE is implemented in a 0.18 μm CMOS process and draws 123 μA current from a 3.3 V supply. The input referred noise and noise efficiency factor (NEF) are 14.6 nV/√Hz and 6.1, respectively.