Maire O'NEill

ML-KEM (FIPS203) and ML-DSA (FIPS204) were two of the first post quantum cryptography schemes to be standardized by the National Institute of Standards and Technology; Both CRYSTALS algorithms utilize modulo reduction, specifically Montgomery reduction. Montgomery reduction traditionally is suited to computing moduli much larger than 32/64-bits and as such, the introduction of a new modulo reduction method published by Thomas Plantard allows for more efficient modulo reduction than Montgomery and Barrett as this new method allows for one less multiplication at the reduction stage. This is achieved by doubling the word size of the values being calculated, meaning the word size of data computed within CRYSTALS-Dilithium doubles from 32-bit to 64-bit and from 16-bit to 32-bit for CRYSTALS-Kyber. In this paper we present the worlds first Plantard ISEs ever that can compute both CRYSTALS-Kyber and CRYSTALS-Dilithium. Utilizing Plantard reduction as a set of Instruction Set Extensions, we are able to reduce the cycle counts required to compute the entire CRYSTALS-Kyber algorithm by up to 19.5% and reduce the cycle counts required to compute CRYSTALS-Dilithium by 26.6% as well as the CRYSTALS-Kyber INTT by 2.66× and the CRYSTALS-Dilithium INTT by 2.42×.

The unpredictable inherent error behavior of approximate computing introduces both new security threats and opportunities to design novel security primitives/strategies. This work proposes a methodology that exploits stochastic timing errors of a pipelined datapath caused by voltage scaling to design an optimized processor-based physical unclonable function (PUF) for approximate computing. To verify the effectiveness of this method, a pipelined arithmetic architecture is implemented at a 45 nm technology node, and voltage scaling is applied to extract PUF bits. With reduced supply voltage, harvested PUF bits show increased uniqueness. Moreover, proposed divergent delay path selection based on intermediary error behavior exhibits improved PUF uniqueness vs an unmodified datapath. A design optimization methodology is applied introducing new PUF metrics - gain (G) and performance power ratio (PPR). Using these metrics, the optimum scaled voltage range is identified for enhanced PUF performance. The optimized PUF shows maximum uniqueness of 49%, and reliability of 92% with a temperature range of -20${\circ }$C to 70${\circ }$C. Further, the proposed PUF with approximate computing achieves markedly improved G and PPR relative to the exact case. With better uniqueness, reliability, and low resource utilization, the proposed PUF methodology is highly suitable for securing approximate computing applications.

Satellite communication networks play a critical role in providing connectivity to remote regions and areas with limited infrastructure. However, their inherently open nature and physical exposure make them particularly susceptible to security threats, including replay, impersonation, and man-in-the-middle attacks. The emergence of quantum computing further undermines the robustness of conventional cryptographic schemes that rely on number-theoretic assumptions. To mitigate these challenges, this article proposes $HBQS$ , a lightweight Post-Quantum authentication framework designed for satellite platforms with limited resources. $HBQS$ integrates physically unclonable functions (PUFs) with hash-based cryptography, leveraging SPHINCS+ digital signatures and SHA-3 hashing to provide secure mutual authentication and session key establishment. The protocol $HBQS$ was implemented and evaluated on embedded hardware platforms, including Raspberry Pi 4.0, PYNQ-Z2 FPGA, and a Dell ground control station. The experimental results demonstrate that $HBQS$ achieves mutual authentication in 0.88 ms, offering an approximately 67% reduction in execution time compared to representative baselines from the prior literature. Entropy analysis confirms that the proposed protocol maintains a high entropy across critical components, with $HBQS$ achieving a signature entropy of 164.63 bits and PUF response entropy of 172.58 bits, indicating strong resistance to statistical and modeling attacks. A formal security analysis conducted within the random oracle model (ROM) demonstrates semantic security against both classical and quantum adversaries. The protocol $HBQS$ shows a significant improvement over existing methods, achieving approximately 67% reduction in computational execution time, approximately 11.5% faster user-side handshake time, approximately 0.6% improvement on the satellite side, and full security coverage across all evaluated security features with only a 21.4% increase in static memory usage as the tradeoff. These findings position $HBQS$ as an efficient, secure, and scalable authentication solution for next-generation satellite communication systems operating in the Post-Quantum era.

CRYSTALS-Dilithium serves as the foundation of the NIST-standardised PQC digital signature scheme, and has been declared as the first recommended digital signature algorithm. However, due to the computational complexity and intricate processing flow of CRYSTALS-Dilithium, two limitations are shown in existing methods: its applicability on resource-constrained devices is limited and the performance reported so far remains relatively low. This paper presents a lightweight yet high-performance hardware architecture that optimises the core computational units of CRYSTALS-Dilithium. First, an iterative dual-Keccak SHA-3 module is proposed, where two cores operate with a 26-cycle offset to accelerate processing without compromising frequency. In addition, the rejection sampler is streamlined by two compact registers for intermediate values and counters, improving efficiency when consuming interleaved SHA-3 outputs. Second, for small bit-width polynomials, we eliminate the first NTT stage via lookup tables and data regrouping, reducing NTT cycles by 11.7% with little hardware overhead. Further hardware savings are achieved by maximising IP core utilisation and simplifying input multiplexers. Furthermore, a compact scheduling strategy ensures that all intermediate storage fits within a single polynomial-sized memory block. On Xilinx Artix-7 FPGAs, the design reduces hardware overhead by 14.2% compared with state-of-the-art lightweight implementations. Across three security levels, KeyGen and Verify are 27.3% and 13.5% faster, respectively, than high-performance prior designs. At level 5, the best-case Sign latency is only 120 µs.

The lattice-based Raccoon scheme is one of the candidates in Round 1 of the National Institute of Standards and Technology (NIST) post-quantum cryptography (PQC) additional digital signatures standardization process. As a scheme with built-in masking features, Raccoon is also a viable candidate for NIST’s Masking Circuit and Threshold Cryptography project. Current Raccoon implementations are limited to software or software-hardware co-designs only and consequently lacking in terms of high throughput performance that hardware implementations can generally promise. To achieve this, we are the first to propose a configurable and high-performance pure hardware architecture for Raccoon. The proposed FPGA architecture features extensive optimizations in key modules for Raccoon such as the modular reduction, polynomial operations, and sampling. The segmentation and loop-based scheduling scheme interacts with the defined BRAM-based memory access pattern to ensure efficient and coherent data flow under the three security levels and two masking modes (non- and first-order masking). Implementation results of Raccoon on an AMD Artix- 7 FPGA device show that our proposed architecture achieves a 1.4–2.1x speedup compared to software implementations and a 20–42x speedup compared to softwarehardware co-designs for the three security levels, despite its hardware area being comparable to that of the lightweight CRYSTALS-Dilithium architecture. Finally, a TVLA test is demonstrated on Raccoon-128 with non-masking and first-order masking to evaluate its resilience to side-channel attacks.

The Module-Lattice-Based Key encapsulation Mechanism (ML-KEM) scheme, which is currently being standardised, is a quantum attack resistant KEM that is based on CRYSTALS-Kyber. CRYSTALS-Kyber is the only Public-key Encryption (PKE)/ KEM scheme selected in the first set of successful candidates as part of the NIST initiated Post-Quantum Cryptography (PQC) process. ML-KEM scheme includes three different security levels, namely security level 1, 3, and 5. In this research, we propose a highly area-time efficient hardware ML-KEM architecture. The architecture comprises three computational layers. The first layer comprises a hash and sampling module; the second layer includes a number theoretic transform (NTT), its inverse (INTT) and a point-wise multiplication (PWM) module; and the third layer comprises addition, compressing and encoding. Intra-layer pipelining and out-of-layer scheduling ensures that either layer 1 or layer 2 operate in the shortest time. In the reduction module, we propose a novel hybrid architecture to obtain the final result within 2 cycles with low area consumption. In the NTT module, the PWM pipelining method is modified and an optimised iterative FIFO access method is adopted to reduce the size of FIFO units by 55% over previous research. Look-up tables are also used to replace the first-stage of the NTT to reduce 8 cycles. Furthermore, the memory unit uses only FIFOs, the size are optimised based on the requirements of the most resource-intensive function in ML-KEM (ML-KEM.CPA.Dec). The results show that the proposed architecture has a 48.2%, 41.2%, and 78.1% reduction in computational time in comparison to previous work for security levels 1, 3, and 5, respectively. In addition, the area of proposed optimised ML-KEM designs is reduced by 73%, 70%, 76% and resulting in an improved area-time (AT) product of 15.8%, 10.7%, and 11.3%, for the Level 1, 3, and 5 security levels respectively, compared with state-of-the-art designs.