Deniz Turkay

We report a two-step thermal evaporation–close space sublimation deposition method for tunable bandgap lead halide perovskites with single junction solar cell efficiencies exceeding 20%. These absorbers are integrated into perovskite–silicon tandem solar cells with stabilized efficiencies of >29%.

Microscale pyramids of silicon solar cells are often considered incompatible with solution-processed perovskite films. Thus, solution processing has mainly been used with submicron pyramids that are buried under thick perovskite films with flattened front surfaces. Yet, while this modification simplifies the fabrication process, it compromises optical performance compared to conformal perovskite films (e.g., obtained by vapor processing). Here, we show that protrusion-free perovskite films can be formed on random pyramids much higher than the film thickness by tailoring the film thickness to match the pyramids' height profile, notably without modifying the pyramid facets. Accordingly, we demonstrate perovskite cells spin-coated on over 2 μm-high random pyramids with electronic performance comparable to those fabricated on flat substrates, and proof-of-concept perovskite-silicon tandem devices with efficiencies reaching 33%. Finally, we show that the undulated films with enhanced conformality enable optical performance superior to flat surfaces, especially upon encapsulation, most relevant to outdoor applications.

Infrared light management is crucial to maximize the optical performance of crystalline Si‐based single junction and tandem solar cells. For this end, a low refractive index dielectric is typically inserted under the rear metal and an electrical contact is obtained locally through the dielectric. However, the realization of such an architecture can require numerous fabrication steps that are time and resource intensive. Herein, a simple approach is proposed in which commercially available, low‐cost SiO₂ nanoparticles (NPs) are spin coated as rear reflectors on pyramid‐textured Si, leaving the pyramid tips locally exposed for direct contact by an electrode without additional patterning. In Si heterojunction solar cells, complementing a 40 nm‐thick indium tin oxide (ITO) layer with the SiO₂‐NPs yields a gain of 0.3 mA cm⁻² in short‐circuit current density compared to that obtained with a bare, 100 nm‐thick ITO layer. Combined with reduced electrical losses, power conversion efficiency gains of 0.5%_abs to 0.3%_abs for single junction Si and perovskite‐Si tandem cells are demonstrated, respectively. Finally, it is shown that the NPs can also be processed on large areas via blade coating and that the process can be further simplified by a change in the fabrication sequence of the SiO₂‐NP and ITO layers.

Silicon heterojunction (SHJ) solar cells have recently reached power conversion efficiencies above 25% with various device architectures and with industrial size (>200 cm ² ) wafers. Yet, for an accurate assessment of the efficiency potential and further development of the technology, the identification of high-performing device configurations, and their detailed analysis is still vital. In this work, we first present an overview of our lab-scale (4 cm ² ) front-junction cells based on n-type wafers with a 24.44% certified efficiency. We report on the key improvements compared with our previously reported devices (i.e., thinner front-side silicon layers and low refractive index rear reflector). Then, we present a detailed power loss analysis, showing that parasitic absorption in the front layer-stack remains a major source of loss despite the recent improvements. Accordingly, we investigate next approaches to circumvent this loss, such as localization of the highly absorbing front layers and switching to a rear-junction architecture. Using numerical calculations, we show that the front-junction configuration can benefit from an efficiency gain of 0.3% _abs with contact localization if considerably low contact resistivities (2 ) are realized for the p-type contact. Even larger gain in efficiency can be achieved by simultaneously switching to a rear-junction architecture and localizing the n-type contact with contact resistivities that are relatively accessible with the current state of the art (up to 0.7% _abs gain for 2 ). Finally, we propose a simple fabrication method for contact localization using shadow masks during depositions of the front-side layers and demonstrate proof-of-concept cells with localized contacts.

Silicon solar cells are approaching their theoretical efficiency limit of 29%. This limitation can be exceeded with advanced device architectures, where two or more solar cells are stacked to improve the harvesting of solar energy. In this work, we devise a tandem device with a perovskite layer conformally coated on a silicon bottom cell featuring micrometric pyramids—the industry standard—to improve its photocurrent. Using an additive in the processing sequence, we regulate the perovskite crystallization process and alleviate recombination losses occurring at the perovskite top surface interfacing the electron-selective contact [buckminsterfullerene (C ₆₀ )]. We demonstrate a device with an active area of 1.17 square centimeters, reaching a certified power conversion efficiency of 31.25%.

Contacts featuring multiple layers of materials in combination with metal electrodes enabled record-high power conversion efficiencies for solar cells in recent years. Minimizing the contact resistivity in these multilayer structures is critical to achieve a high device performance and rapid characterization methods are crucial for the experimental analysis of this aspect. However, commonly used test methods and the associated mathematical formulations to extract contact resistivity are not designed for samples with multiple layers. In this work, we analyze formulations describing the resistance measured in ohmic multilayer test structures, which are used to fit and extract an unknown contact resistivity. We focus on a contacting scheme with circular electrodes, commonly named after Cox and Strack (CS), and analyze a material configuration consisting of a thick Si substrate fully coated with a thin conductive layer (CL). We demonstrate the applicability and accuracy of various spreading resistance models (SRMs) from the literature to calculate the measured resistance and compare the results with those obtained by the finite element method (FEM). Moreover, we present a new SRM with a closed-form expression for the measured resistance, which is computationally more efficient than the existing SRMs. Last, we demonstrate the applicability of this model in experiments with ( ${n}$ )c-Si/( ${i}$ )a-Si:H/( ${n}$ )a-Si:H/indium tin oxide (ITO) test structures.