Tianyang Chen
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Tianyang Chen has a total of 15 co-authors. Here are the top co-authors by number of shared publications:
- Junjie Zhang
Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai University, Shanghai, China
4 shared publications - Yingchun Li
Key laboratory of Specialty Fiber Optics and Optical Access Networks, Joint International Research Laboratory of Specialty Fiber Optics and Advanced Communication, Shanghai University, Shanghai 200444, China
2 shared publications - Zhijie Wang
Key laboratory of Specialty Fiber Optics and Optical Access Networks, Joint International Research Laboratory of Specialty Fiber Optics and Advanced Communication, Shanghai University, Shanghai 200444, China
2 shared publications - Bingyao Cao
The Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai Institute for Advanced Communication and Data Science, Shanghai University, Shanghai 200072, China
1 shared publication - Dan Yang
Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai Institute for Advanced Communication and Data Science, Shanghai University, Shanghai 200072, China
1 shared publication - Hu Li
Key laboratory of Specialty Fiber Optics and Optical Access Networks, Joint International Research Laboratory of Specialty Fiber Optics and Advanced Communication, Shanghai University, Shanghai 200444, China
1 shared publication
Latest Publications
- Open Access
An Energy-Efficient FPGA-Based Real-Time IMDD OFDM-PON Enabled by an Efficient FFT
For the first time, a highly energy-efficient 32-parallel 64-point FFT scheme for IMDD OFDM-PON is proposed and implemented on a Xilinx ML605 platform. By experimentally verifying the power consumption model for the FPGA logic resources utilized in the FFT, the relationship between FFT calculating consumption and FPGA logic resource usage is established. Based on this relationship, we derive a resource selection principle for the FFT bit resolution optimization to minimize power consumption under different levels of received optical power. Consequently, the proposed FFT achieves a 76.1% reduction in power consumption compared to the traditional Spiral FFT at a received optical power of −21 dBm. Based on the proposed FFT, the real-time OFDM-PON receiver power consumption can save up to 43% compared with traditional OFDM-PON system.
Open AccessAn Energy-Efficient FPGA-Based Real-Time IMDD OFDM-PON Enabled by an Efficient FFT
For the first time, a highly energy-efficient 32-parallel 64-point FFT scheme for IMDD OFDM-PON is proposed and implemented on a Xilinx ML605 platform. By experimentally verifying the power consumption model for the FPGA logic resources utilized in the FFT, the relationship between FFT calculating consumption and FPGA logic resource usage is established. Based on this relationship, we derive a resource selection principle for the FFT bit resolution optimization to minimize power consumption under different levels of received optical power. Consequently, the proposed FFT achieves a 76.1% reduction in power consumption compared to the traditional Spiral FFT at a received optical power of −21 dBm. Based on the proposed FFT, the real-time OFDM-PON receiver power consumption can save up to 43% compared with traditional OFDM-PON system.
- Open Access
Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA
The TCP protocol is a connection-oriented and reliable transport layer communication protocol which is widely used in network communication. With the rapid development and popular application of data center networks, high-throughput, low-latency, and multi-session network data processing has become an immediate need for network devices. If only a traditional software protocol stack is used for processing, it will occupy a large amount of CPU resources and affect network performance. To address the above issues, this paper proposes a double-queue storage structure for a 10G TCP/IP hardware offload engine based on FPGA. Furthermore, a TOE reception transmission delay theoretical analysis model for interaction with the application layer is proposed, so that the TOE can dynamically select the transmission channel based on the interaction results. After board-level verification, the TOE supports 1024 TCP sessions with a reception rate of 9.5 Gbps and a minimum transmission latency of 600 ns. When the TCP packet payload length is 1024 bytes, the latency performance of TOE’s double-queue storage structure improves by at least 55.3% compared to other hardware implementation approaches. When compared with software implementation approaches, the latency performance of TOE is only 3.2% of the software approaches.
Open AccessLow Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA
The TCP protocol is a connection-oriented and reliable transport layer communication protocol which is widely used in network communication. With the rapid development and popular application of data center networks, high-throughput, low-latency, and multi-session network data processing has become an immediate need for network devices. If only a traditional software protocol stack is used for processing, it will occupy a large amount of CPU resources and affect network performance. To address the above issues, this paper proposes a double-queue storage structure for a 10G TCP/IP hardware offload engine based on FPGA. Furthermore, a TOE reception transmission delay theoretical analysis model for interaction with the application layer is proposed, so that the TOE can dynamically select the transmission channel based on the interaction results. After board-level verification, the TOE supports 1024 TCP sessions with a reception rate of 9.5 Gbps and a minimum transmission latency of 600 ns. When the TCP packet payload length is 1024 bytes, the latency performance of TOE’s double-queue storage structure improves by at least 55.3% compared to other hardware implementation approaches. When compared with software implementation approaches, the latency performance of TOE is only 3.2% of the software approaches.
- Open Access
High Throughput Priority-Based Layered QC-LDPC Decoder with Double Update Queues for Mitigating Pipeline Conflicts
A high-throughput layered decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes is required for communication systems. The preferred way to improve the throughput is to insert pipeline stages and increase the operating frequency, which suffers from pipeline conflicts at the same time. A priority-based layered schedule is proposed to keep the updates of log-likelihood ratios (LLRs) as frequent as possible when pipeline conflicts happen. To reduce pipeline conflicts, we also propose double update queues for layered decoders. The proposed double update queues improve the percentage of updated LLRs per iteration. Benefitting from these, the performance loss of the proposed decoder for the fifth generation (5G) new radio (NR) is reduced from 0.6 dB to 0.2 dB using the same quantization compared with the state-of-the-art work. As a result, the throughput of the proposed decoder improved up to 2.85 times when the signal-to-noise ratio (SNR) was equal to 5.9 dB.
Open AccessHigh Throughput Priority-Based Layered QC-LDPC Decoder with Double Update Queues for Mitigating Pipeline Conflicts
A high-throughput layered decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes is required for communication systems. The preferred way to improve the throughput is to insert pipeline stages and increase the operating frequency, which suffers from pipeline conflicts at the same time. A priority-based layered schedule is proposed to keep the updates of log-likelihood ratios (LLRs) as frequent as possible when pipeline conflicts happen. To reduce pipeline conflicts, we also propose double update queues for layered decoders. The proposed double update queues improve the percentage of updated LLRs per iteration. Benefitting from these, the performance loss of the proposed decoder for the fifth generation (5G) new radio (NR) is reduced from 0.6 dB to 0.2 dB using the same quantization compared with the state-of-the-art work. As a result, the throughput of the proposed decoder improved up to 2.85 times when the signal-to-noise ratio (SNR) was equal to 5.9 dB.
- Open Access
Low-Complexity Sampling Frequency Offset Estimation and Compensation Scheme for OFDM-Based UWOC System
In this paper, a simple sampling frequency offset (SFO) estimation and compensation scheme based on two phase-conjugated pilots is proposed and experimentally demonstrated in an OFDM-based underwater wireless optical communication (UWOC) system. The phase shift is obtained by simple multiplication for phase-conjugated pilots, and the results are averaged to perform more accurate phase estimation. The experimental results show that the estimation offset is limited within ±3 ppm when the SFO ranges from −1000 ppm to +1000 ppm over a 1 m tap water channel. Moreover, with the help of the proposed scheme, up to ±300 ppm SFO can be well-compensated with error vector magnitude (EVM) penalties below 1 dB after 1 m underwater transmission. In addition, the results demonstrate that, compared with the ideal case without SFO, our proposed SFO compensation scheme can provide nearly negligible bit error rate (BER) penalties in saltwater with the highly scattering property.
Open AccessLow-Complexity Sampling Frequency Offset Estimation and Compensation Scheme for OFDM-Based UWOC System
In this paper, a simple sampling frequency offset (SFO) estimation and compensation scheme based on two phase-conjugated pilots is proposed and experimentally demonstrated in an OFDM-based underwater wireless optical communication (UWOC) system. The phase shift is obtained by simple multiplication for phase-conjugated pilots, and the results are averaged to perform more accurate phase estimation. The experimental results show that the estimation offset is limited within ±3 ppm when the SFO ranges from −1000 ppm to +1000 ppm over a 1 m tap water channel. Moreover, with the help of the proposed scheme, up to ±300 ppm SFO can be well-compensated with error vector magnitude (EVM) penalties below 1 dB after 1 m underwater transmission. In addition, the results demonstrate that, compared with the ideal case without SFO, our proposed SFO compensation scheme can provide nearly negligible bit error rate (BER) penalties in saltwater with the highly scattering property.