Jaeyong Lee

This paper presents a fully integrated three-stage stacked power amplifier (PA) operating in the K-/Ka-band, fabricated using a TSMC 65 nm CMOS process for fifth-generation (5G) millimeter-wave applications. To improve the output power without sacrificing reliability, a two-stacked-FET configuration is adopted in the power stage, which distributes the voltage stress across series-connected transistors and permits a higher supply voltage than a conventional cascode structure. A differential topology with capacitive neutralization is employed in both the common-source driver stage and the stacked power stage. The neutralization capacitance is determined from a stability- and gain-oriented analysis based on the Rollett stability factor (K) and the maximum available gain (MAG), which clarifies the trade-off between feedback cancelation and wideband gain flatness over the operating band. The fabricated PA occupies a total chip area of 0.51 mm², including pads, with a core area of 0.18 mm². The measurement results demonstrate a measured 3 dB bandwidth of 6.7 GHz from 24.6 GHz to 31.3 GHz, a peak small-signal gain of 32.9 dB, a saturated output power of 20.8 dBm, an output 1 dB compression point of 16 dBm, and a peak power-added efficiency of 20.4% at 28.5 GHz. Over the 26–30 GHz range in which the large-signal characterization was performed, the saturated output power varies by less than 1 dB and the efficiency by less than 2 percentage points, indicating that the combination of capacitive neutralization and stacked-FET operation provides a compact solution for wideband K-/Ka-band CMOS power amplification.

This paper presents a hybrid-oxide (HO) stacked-FET architecture aimed at enhancing the output power of high-frequency CMOS power amplifiers. In the proposed topology, a thin-gate-oxide transistor is employed as the common-source (CS) device, while a thick-gate-oxide transistor is used as the common-gate (CG) device within the stacked-FET configuration. By leveraging the distinct breakdown characteristics of each device, the proposed structure redistributes the voltage stress across the stack, enabling higher voltage swings while reducing the number of stacked transistors. The gate impedance control (GIC) capacitor is optimally designed to achieve the desired voltage distribution ratio without overstressing individual devices. A theoretical analysis is conducted to derive the optimal gate impedance control (GIC) capacitance required to ensure proper device operation under unequal voltage drops. A prototype power amplifier was implemented using a 65-nm bulk CMOS process. The fabricated chip occupies an area of 1.04 × 0.60 mm², with a core area of 0.90 × 0.26 mm². The amplifier operates over the 8–13 GHz frequency band and achieves an output 1-dB compression point (OP1dB) of 25.7 dBm and a peak power-added efficiency (PAE) of 26.5% at 10 GHz. Under a 64-QAM modulated input with 100 MHz bandwidth and 9.6 dB peak-to-average power ratio (PAPR), the amplifier delivers an average output power (PAVG) of 17.1 dBm and average PAE of 8.4%, with an error vector magnitude (EVM) of –25 dB. These results demonstrate that the proposed architecture offers a promising design alternative for reducing complexity while maintaining high output power in RF CMOS power amplifier applications.

This work presents a wideband, low-power single-pole double-throw (SPDT) switch implemented in a 65-nm RFCMOS process. A π-type matching network is introduced at the common port (P_TR) to simultaneously improve insertion loss and isolation, extending the operating range from approximately 20 GHz to 60 GHz. To suppress core-area growth, transistors are placed inside the inductor, and the layout is arranged to minimize magnetic coupling between the inductor and the transistors so that high-frequency operation remains stable. Measurements show insertion loss ≤ 2.3 dB, return loss ≥ 12 dB, and isolation ≥ 26.8 dB over DC-40 GHz. The input 1-dB compression point is about 9-10 dBm, indicating suitability for medium-power applications. These results indicate an SPDT switch that achieves wide bandwidth, low loss, high isolation, and area efficiency.

In this study, we present the design of a single-pole double-throw (SPDT) switch for Sub-6 GHz applications, implemented using a 500-nm GaAs BiFET process. To enhance power handling capability, multi-gate transistors are selectively employed. The frequency characteristics of return loss, insertion loss, and isolation are analyzed through an equivalent circuit model. Based on this analysis, we propose a design methodology that optimizes transistor on-resistance and parasitic capacitance for the target frequency range, thereby improving power handling, insertion loss, return loss, and isolation. The fabricated switch is evaluated across an operating frequency range of 3.0-5.0 GHz. In Tx mode, the input P1dB exceeds 38.1 dBm at 4.0 GHz. The measured insertion loss and isolation in Tx mode are below 0.38 dB and above 36.6 dB, respectively. In Rx mode, insertion loss remains below 0.38 dB, while isolation exceeds 35.0 dB.

This paper investigates and evaluates a compact, high-Q glass transformer with a 3D spiral structure that offers low loss and high area efficiency. Furthermore, we designed a CMOS power amplifier (PA) with an output-matching network implemented using an off-chip high-Q glass transformer to validate its operation. Two transformer types were developed: a five-port transformer with a center-tap and a four-port transformer without a center tap. The high-Q property of the transformer leads to low loss and tight coupling, as evidenced by an increase in maximum available gain (MAG). Compared with an integrated CMOS transformer, the high-Q transformer exhibits significantly lower loss while maintaining similar area and inductance, despite being an external component. A test PA comprising the CMOS PA and the off-chip transformer was evaluated with simulations and measurements, and it was also compared with a fully integrated PA at the simulation level to verify performance improvements. The proposed PA achieved a saturation power of 29.8 dBm, which was 1.7 dB higher than that of the fully integrated PA. The PAE also improved by 11 percentage points, from 32.1% to 43.1% in simulation. The results show substantial performance gains in simulation, while the total area increases only slightly. Measurements show the same trend as the simulations; with shorter bond-wire lengths, the measured results are expected to approach the simulated performance. These findings demonstrate the feasibility of an ultra-compact CMOS–off-chip hybrid PA that delivers high performance while maintaining a footprint comparable to that of a fully integrated PA, enabling applications in compact devices including mobile products.

In this study, we design a CMOS-based active phase shifter operating at 26–30 GHz. In order to improve the performance of the phase shifter by suppressing the signal imbalance in the phase shifter, a polyphase filter (PPF) layout with a symmetrical structure is proposed. After that, the imbalance of the output signal due to the imbalance of the input signal of the symmetrical PPF is analyzed from the perspective of the magnitude, phase, and impedance of the input signal. Based on the analyzed results, a structure of an active input balun is proposed to suppress the magnitude and phase imbalance of the PPF input signal. An inductor is added to one of the differential output nodes of the proposed active input balun to suppress the output signal imbalance of the active input balun. The feasibility of the proposed symmetric PPF and active input balun is verified from simulation and measurement results. The proposed active phase shifter is fabricated through a 65-nm RFCMOS process. Under power gain conditions of –11, –10, –9, and –8 dB, the rms phase error and rms magnitude error are measured to be lower than 2.57° and 0.44 dB, respectively. Here, the resolution of the phase variation is set to 5.625°.

This paper presents the differential-to-single-ended load-modulated (DISEL)-power amplifier, a transformer-based dual-mode Ka-band CMOS power amplifier designed to enhance power-added efficiency (PAE) under output back-off conditions while maintaining high output power. Implemented in a 65-nm RFCMOS process, the DISEL-power amplifier employs a reconfigurable architecture that switches between differential and single-ended modes according to output power levels without requiring complex impedance matching networks. In high-power mode, the power amplifier operates as a fully differential three-stacked FET structure to deliver high output power, while in low-power mode, one differential branch is selectively deactivated to increase the load impedance seen by the active path, thereby improving PAE under output back-off conditions while maintaining linearity. Measurement results with a 28.0 GHz continuous wave input demonstrate a saturated output power exceeding 23.1 dBm and a peak PAE of 28.5% in high-power mode. Furthermore, at a 10 dB output back-off point relative to the high-power mode, the low-power mode achieves a 2.3 percentage point improvement in PAE. These results verify that the proposed DISEL-power amplifier structure can maintain high output power while improving PAE under output back-off conditions.