Li Zhou

Radar signal sorting (RSS) is a critical technology for electronic support measures (ESM) systems to achieve radar identification and threat assessment. However, RSS encounters significant challenges in complex electromagnetic environments, primarily characterized by overlapping pulse description word (PDW) parameters from multiple emitters, non-stationary pulse repetition interval (PRI) modulations, and the coexistence of false alarm pulses (FAPs) and missing pulses (MPs). This article proposes a radar signal sorting method via cascaded pulse parameters, which integrates PDW-based spatial clustering with PRI-based temporal validation. First, pulses are mapped into a normalized threedimensional feature space constructed from carrier frequency (CF), pulse width (PW), and direction of arrival (DOA). Subsequently, an adaptive outlier detection mechanism employing the relative local outlier factor (RLOF) identifies and eliminates false alarm pulses through natural neighbor analysis. Next, initial pulse sorting is performed using density clustering with adaptively determined parameters. The cluster validation stage merges over-segmented clusters by evaluating inter-cluster correlations and boundary connectivity to address over-clustering. Finally, a two-dimensional PRI plane mapping technique incorporating statistical distribution characteristics performs further refinement of clusters, identifying authentic PRIs and extracting corresponding pulse sequences to address underclustering. Experimental results demonstrate that the proposed method achieves sorting accuracy exceeding 96% under non-ideal conditions involving overlapping PDW parameters, FAPs, MPs, and non-stationary PRI modulations. The proposed method operates autonomously without requiring prior knowledge or manual parameter configuration.

Radar signal sorting (RSS) is a key technology in electronic support measures (ESM) systems, laying the foundation for subsequent processes such as radar identification and spatial localization. However, implementing automated RSS without prior knowledge poses significant challenges in complex electromagnetic environments characterized by densely interleaved multisource radar signals that involve coexisting false alarm pulses (FAPs) and missing pulses (MPs). This article proposes an adaptive RSS method via enhanced density peak clustering (RSSCO-EDPC). The method, taking pulse description words (PDWs) as input data, proceeds through several sequential stages. Firstly, we adaptively determine the optimal radiation factor via potential entropy minimization in the data field, and eliminate false alarm pulses using a standardized potential energy threshold of 1. Secondly, local density and relative distance computations are optimized via natural nearest neighbors to construct decision graphs. Polynomial regression is used to isolate cluster centers by analyzing the decision graphs. A three-step allocation algorithm is then employed to assign core, non-core, and remaining pulses. Lastly, a cluster merging mechanism integrating natural neighborhood sets is implemented to address over-clustering, which arises from a radar being represented by several clusters. Comprehensive evaluations demonstrate that the proposed method maintains sorting accuracy exceeding 95% under severe non-ideal conditions while eliminating over-clustering, requiring neither prior knowledge nor manual intervention.

Single Event Upsets (SEUs) in Commercial Off-The-Shelf (COTS) Software-Defined Radios (SDRs) are frequent in a erospace applications, especially in GEO (Geostationary Orbit) orbit during severe solar activity, and can lead to unexpected register corruption and communication failures. This work presents a purely software-based Fault Detection, Isolation, and Recovery (FDIR) framework tailored for the AD936x RF agile transceiver, requiring no hardware modifications. The proposed method classifies all device registers into four impact categories and applies dedicated scrubbing strategies—standard refresh, masked refresh, procedural refresh, and forced refresh—combined with real-time register health monitoring and adaptive recovery actions. Fault injection experiments comprising 10,000 diverse test cases achieved 100% fault coverage for the tested scenarios, with an average recovery time of 0.75 s for typical SEUs and a guaranteed worst-case recovery under 4.4 s for critical failures, while maintaining a CPU load below 1.3%. The approach ensures continuous SDR operation under SEU events and offers a scalable, lightweight, and cost-effective reliability enhancement for CubeSats and other resource-constrained aerospace platforms.

Real-time lossless image compression based on the JPEG-LS algorithm is in high demand for critical missions such as satellite remote sensing and space exploration due to its excellent balance between complexity and compression rate. However, few researchers have made appropriate modifications to the JPEG-LS algorithm to make it more suitable for high-speed hardware implementation and application to Bayer pattern data. This paper addresses the current limitations by proposing a real-time lossless compression system specifically tailored for Bayer pattern images from spaceborne cameras. The system integrates a hybrid encoding strategy modified from JPEG-LS, combining run-length encoding, predictive encoding, and a non-encoding mode to facilitate high-speed hardware implementation. Images are processed in tiles, with each tile’s color channels processed independently to preserve individual channel characteristics. Moreover, potential error propagation is confined within a single tile. To enhance throughput, the compression algorithm operates within a 20-stage pipeline architecture. Duplication of computation units and the introduction of key-value registers and a bypass mechanism resolve structural and data dependency hazards within the pipeline. A reorder architecture prevents pipeline blocking, further optimizing system throughput. The proposed architecture is implemented on a XILINX XC7Z045-2FFG900C SoC (Xilinx, Inc., San Jose, CA, USA) and achieves a maximum throughput of up to 346.41 MPixel/s, making it the fastest architecture reported in the literature.

The error correction capability of the RS(255,223) code has been significantly enhanced compared to that of the RS(256,252) code, making it the preferred choice for the next generation of onboard solid-state recorders (O-SSRs). With the application of non-volatile double data rate (NV-DDR) interface technology in O-SSRs, instantaneous transmission rates of up to 1 Gbps per data I/O interface can be achieved. This development imposes higher requirements on the encoding throughput of RS encoders. For RS(255,223) encoders, throughput improvement is limited by the structures of serial architectures. The algorithm’s inherent characteristics restrict the depth of pipelining. In contrast, parallel solutions face bottlenecks in resource efficiency. To address these challenges, an interleaved pipelined architecture is proposed. By integrating interleaving technology within the pipeline, the structure overcomes the limitations of serial architectures. Using this architecture, a 36-stage pipelined RS(255,223) encoder is implemented. The throughput is greatly enhanced, and the radiation tolerance is also improved due to the application of interleaving techniques. The RS(255,223) encoder performance was evaluated on the Xilinx XC7K325T platform. The results confirm that the proposed architecture can support high data rates and provide effective error correction. With an 8-bit symbol size, a single encoder achieved throughput of 3.043 Gbps, making it highly suitable for deployment in future space exploration missions.

Lossless image compression plays a vital role in improving data storage and transmission efficiency without compromising data integrity. However, the throughput of current lossless compression and decompression systems remains limited and is unable to meet the growing demands of high-speed data transfer. To address this challenge, a previously proposed hybrid lossless compression and decompression algorithm has been implemented on an FPGA platform. This implementation significantly improves processing speed and efficiency. A multi-core system architecture is introduced, utilizing the processing system (PS) and programmable logic (PL) of a Xilinx Zynq-706 evaluation board. The PS handles coordination. The PL performs compression and decompression using multiple cores. Each core can process up to eight image tiles at the same time. The compression process is designed with a four-stage pipeline, and decompression is managed by a dynamic state machine to ensure optimized control. The parallel architecture and innovative algorithm design enable high-throughput operation, achieving compression and decompression rates of 480 Msubpixels/s and 372 Msubpixels/s, respectively. Through this work, a practical and high-performance solution for real-time lossless image compression is demonstrated.

Sorting in sequential data mining is significantly improved through hardware acceleration, which becomes essential as data volume and complexity increase. This paper presents a scalable hybrid sorting network that maintains or improves performance while reducing computational load and hardware requirements. The network is composed of the pre-comparison odd–even sorting network (P-OESN) and the bidirectional insertion sorting network (BISN). A pre-comparison layer is introduced to the original OESN. This layer aims to place larger values in the first half of the input sequence and smaller values in the latter half. The number of iterations is reduced when the P-OESN transitions from fully parallel execution to iterative execution. A novel pipelined BISN architecture is proposed, which leads to enhanced operating frequency and throughput. The experimental results show that the pre-comparison layer reduces the number of iterations by 6% to 50%. Throughput is improved by more than four times, and operating frequency is increased by more than two times due to the pipelined BISN. The proposed hybrid sorting network reduces sorting time or resource usage, while enabling the sorting of large-scale data sets that other methods cannot support.

The data acquisition rate of electromagnetic spectrum sensors is exceedingly high. However, the throughput of current high-speed spaceborne solid-state recorders (S-SSR) remains relatively low, making it difficult for the data to be fully stored. To address this issue, a novel architecture for a high-speed S-SSR is introduced in this study. The throughput of the S-SSR is primarily limited by three factors: the performance of the error-checking algorithm, the inability of a single FPGA to support the parallel expansion of too many Flash chips due to its limited effective I/O pins, and the efficiency of FLASH control. In the proposed architecture, a 10-stage pipelined RS(252,256) code is implemented. Data are distributed and stored in different memory regions controlled by separate FPGAs. Interleaved storage, multi-plane, and cache operation FLASH control module are also employed to resolve these bottlenecks. To further increase the throughput of the S-SSR, the system clock distribution has been optimized. In addition, interleaved encoding technology has been applied to improve radiation resistance and ensure data integrity. The performance of the system was evaluated on the Xilinx XC7K325T platform. The results confirm that the architecture is capable of handling high data rates and effectively correcting errors. The system can achieve a throughput of 46.8948 Gbps, making it suitable for future deployment in space exploration missions.

The eigen-decomposition of a covariance matrix is a key step in the Direction of Arrival (DOA) estimation algorithms such as subspace classes. Eigen-decomposition using the parallel Jacobi algorithm implemented on FPGA offers excellent parallelism and real-time performance. Addressing the high complexity and resource consumption of the traditional parallel Jacobi algorithm implemented on FPGA, this study proposes an improved FPGA-based parallel Jacobi algorithm for eigen-decomposition. By analyzing the relationship between angle calculation and rotation during the Jacobi algorithm decomposition process, leveraging parallelism in the data processing, and based on the concepts of time-division multiplexing and parallel partition processing, this approach effectively reduces FPGA resource consumption. The improved parallel Jacobi algorithm is then applied to the classic DOA estimation algorithm, the MUSIC algorithm, and implemented on Xilinx’s Zynq FPGA. Experimental results demonstrate that this parallel approach can reduce resource consumption by approximately 75% compared to the traditional method but introduces little additional time consumption. The proposed method in this paper will solve the problem of great hardware consumption of eigen-decomposition based on FPGA in DOA applications.