Jong-Woo Kim
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Jong-Woo Kim has a total of 10 co-authors. Here are the top co-authors by number of shared publications:
- Byeong-Kwon Ju
School of Electrical Engineering Korea University Seoul South Korea
3 shared publications - Min Kyu Yang
Department of Artificial Intelligence Semiconductor Engineering Sahmyook University Seoul Republic of Korea
3 shared publications - Hyun Kyu Seo
Artificial Intelligence Convergence Research Lab, Sahmyook University, Seoul 01795, Korea
2 shared publications - Minsoo Park
Artificial Intelligence Convergence Research Lab, Sahmyook University, Seoul 01795, Korea
2 shared publications - Su Yeon Lee
Artificial Intelligence Convergence Research Lab, Sahmyook University, Seoul, Republic of Korea
2 shared publications Dong-Hyun Baek
1 shared publication
Latest Publications
- Open Access
Highly Reliable Ovonic Threshold Switch with TiN/GeTe/TiN Structure
A new architecture has become necessary owing to the power consumption and latency problems of the von Neumann architecture. A neuromorphic memory system is a promising candidate for the new system as it has the potential to process large amounts of digital information. A crossbar array (CA), which consists of a selector and a resistor, is the basic building block for the new system. Despite the excellent prospects of crossbar arrays, the biggest obstacle for them is sneak current, which can cause a misreading between the adjacent memory cells, thus resulting in a misoperation in the arrays. The chalcogenide-based ovonic threshold switch (OTS) is a powerful selector with highly nonlinear I–V characteristics that can be used to address the sneak current problem. In this study, we evaluated the electrical characteristics of an OTS with a TiN/GeTe/TiN structure. This device shows nonlinear DC I–V characteristics, an excellent endurance of up to 109 in the burst read measurement, and a stable threshold voltage below 15 mV/dec. In addition, at temperatures below 300 °C, the device exhibits good thermal stability and retains an amorphous structure, which is a strong indication of the aforementioned electrical characteristics.
Open AccessHighly Reliable Ovonic Threshold Switch with TiN/GeTe/TiN Structure
A new architecture has become necessary owing to the power consumption and latency problems of the von Neumann architecture. A neuromorphic memory system is a promising candidate for the new system as it has the potential to process large amounts of digital information. A crossbar array (CA), which consists of a selector and a resistor, is the basic building block for the new system. Despite the excellent prospects of crossbar arrays, the biggest obstacle for them is sneak current, which can cause a misreading between the adjacent memory cells, thus resulting in a misoperation in the arrays. The chalcogenide-based ovonic threshold switch (OTS) is a powerful selector with highly nonlinear I–V characteristics that can be used to address the sneak current problem. In this study, we evaluated the electrical characteristics of an OTS with a TiN/GeTe/TiN structure. This device shows nonlinear DC I–V characteristics, an excellent endurance of up to 109 in the burst read measurement, and a stable threshold voltage below 15 mV/dec. In addition, at temperatures below 300 °C, the device exhibits good thermal stability and retains an amorphous structure, which is a strong indication of the aforementioned electrical characteristics.
- Open Access
Improvement in Electrical Stability of a-IGZO TFTs Using Thinner Dual-Layer Dielectric Film
This study investigates the effect of gate insulators on thin-film transistors (TFTs) using an amorphous InGaZnO4 (a-IGZO) channel layer. TFTs with single-layer Ta2O5 and dual-layer Ta2O5/SiO2 gate insulators were fabricated on a glass substrate. An evaluation of the insulating film using the MIM (Metal-Insulator-Metal) structure confirmed its electrical characteristics. Microscopic imaging showed that the dual-layer Ta2O5/SiO2 dielectric significantly improved surface characteristics. A reduction in the leakage current, better on/off ratios, and a decreased subthreshold swing (SS) compared to a single-layer Ta2O5 dielectric were reported. The dual-layer insulator composed of SiO2/Ta2O5 was highly effective in improving device characteristics.
Open AccessImprovement in Electrical Stability of a-IGZO TFTs Using Thinner Dual-Layer Dielectric Film
This study investigates the effect of gate insulators on thin-film transistors (TFTs) using an amorphous InGaZnO4 (a-IGZO) channel layer. TFTs with single-layer Ta2O5 and dual-layer Ta2O5/SiO2 gate insulators were fabricated on a glass substrate. An evaluation of the insulating film using the MIM (Metal-Insulator-Metal) structure confirmed its electrical characteristics. Microscopic imaging showed that the dual-layer Ta2O5/SiO2 dielectric significantly improved surface characteristics. A reduction in the leakage current, better on/off ratios, and a decreased subthreshold swing (SS) compared to a single-layer Ta2O5 dielectric were reported. The dual-layer insulator composed of SiO2/Ta2O5 was highly effective in improving device characteristics.
- Open Access
- 28 September 2022
- Published by MDPI AG in Electronics
- Vol. 11 (19) , 3094
Microwave-Assisted Annealing Method for Low-Temperature Fabrication of Amorphous Indium-Gallium-Zinc Oxide Thin-Film Transistors
Compared with conventional silicon-based semiconductors, amorphous oxide semiconductors present several advantages, including the possibility of room-temperature fabrication, excellent uniformity, high transmittance, and high electron mobility. Notably, the application of oxide semiconductors to flexible electronic devices requires a low-temperature fabrication process. However, for the realization of semiconductor characteristics and stable products, the fabrication process requires annealing at temperatures of 300 °C or higher. To address this, a low-temperature microwave annealing method, which improves the electrical characteristics of a transistor and reduces the production time compared with the conventional annealing method, is presented herein. Microwave annealing is a well-known method of annealing that minimizes the heat energy transferred to a substrate via instantaneous heat transfer through the vibrations of the lattice in the material during microwave irradiation and is suitable as a low-temperature annealing method. In this study, we evaluate the electrical characteristics of devices subjected to conventional annealing at 200 °C and 300 °C for 1 h and microwave annealing at 200 °C for 10 min. For the device subjected to microwave annealing at 200 °C for 10 min, the threshold voltage, current on/off ratio, subthreshold swing, and saturation mobility are 13.9 V, 1.14 × 105, 3.05 V/dec, and 4.23 cm2/Vs, respectively. These characteristic results are far superior to the characteristic results of the device subjected to conventional annealing at 200 °C for 1 h and are equivalent to those of the device treated at 300 °C for 1 h. Thus, this study develops a more effective annealing method, which facilitates low-temperature fabrication in a reduced period.- 28 September 2022
- Published by MDPI AG in Electronics
- Vol. 11 (19) , 3094
Open AccessMicrowave-Assisted Annealing Method for Low-Temperature Fabrication of Amorphous Indium-Gallium-Zinc Oxide Thin-Film Transistors
Compared with conventional silicon-based semiconductors, amorphous oxide semiconductors present several advantages, including the possibility of room-temperature fabrication, excellent uniformity, high transmittance, and high electron mobility. Notably, the application of oxide semiconductors to flexible electronic devices requires a low-temperature fabrication process. However, for the realization of semiconductor characteristics and stable products, the fabrication process requires annealing at temperatures of 300 °C or higher. To address this, a low-temperature microwave annealing method, which improves the electrical characteristics of a transistor and reduces the production time compared with the conventional annealing method, is presented herein. Microwave annealing is a well-known method of annealing that minimizes the heat energy transferred to a substrate via instantaneous heat transfer through the vibrations of the lattice in the material during microwave irradiation and is suitable as a low-temperature annealing method. In this study, we evaluate the electrical characteristics of devices subjected to conventional annealing at 200 °C and 300 °C for 1 h and microwave annealing at 200 °C for 10 min. For the device subjected to microwave annealing at 200 °C for 10 min, the threshold voltage, current on/off ratio, subthreshold swing, and saturation mobility are 13.9 V, 1.14 × 105, 3.05 V/dec, and 4.23 cm2/Vs, respectively. These characteristic results are far superior to the characteristic results of the device subjected to conventional annealing at 200 °C for 1 h and are equivalent to those of the device treated at 300 °C for 1 h. Thus, this study develops a more effective annealing method, which facilitates low-temperature fabrication in a reduced period.