Ghil-Geun Oh
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Ghil-Geun Oh has a total of 5 co-authors. Here are the top co-authors by number of shared publications:
B. Lee
Product and Test Engineering Team Foundry Division Samsung Electronics, Co. Ltd Hwa‐sung Republic of Korea
1 shared publication- Jun-Geol Baek
Department of Industrial and Management Engineering, Korea University, Seoul, South Korea
1 shared publication Y.‐W. Lee
Product and Test Engineering Team Foundry Division Samsung Electronics, Co. Ltd Hwa‐sung Republic of Korea
1 shared publication- Yongeun Jang
Department of Industrial and Management Engineering, Korea University, Seoul, South Korea
1 shared publication - Yonggon Jung
Department of Industrial and Management Engineering, Korea University, Seoul, South Korea
1 shared publication
Latest Publications
- Open Access
- 10 June 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 14, 90319-90333
A Gated Attention-Based Semi-Supervised Learning Framework for Label-Scarce Tabular Data
Tabular data is a data format commonly used in various industries, including finance, medical services, and manufacturing. However, deep learning research for this data type has lagged behind the progress seen in computer vision and natural language processing. Real-world applications often face severe label scarcity due to high labeling costs. Traditional Gradient Boosting Decision Trees (GBDTs) and existing deep learning architectures struggle to achieve high predictive performance under these constraints. This study proposes the Gated Attention Tabular Encoder (GATE) and a two-stage semi-supervised learning pipeline. GATE effectively captures complex feature interactions by using global context from self-attention to dynamically regulate the flow of feature information. The proposed pipeline uses a teacher-student self-distillation framework to extract robust representations from unlabeled data. Then, it employs SoftNCA-based metric learning alongside high-confidence pseudo-labeling to optimize the embedding space with minimal labeled instances. Experimental results on public benchmark data showed that the proposed framework consistently achieved superior average performance across all label-ratio scenarios. The framework achieved an average accuracy of 62.23% with only 1% of the labeled data. It also achieved the highest average accuracy of 89.26% in a fully supervised setting, confirming its universal competitiveness. Through additional experiments, we confirmed that the proposed pipeline constructs a structurally superior representation space and achieves greater class separation compared to supervised learning models. In addition, in terms of computational efficiency, the proposed pipeline achieved this performance by using only 50% of the training parameters and 33% of the FLOPs compared to the comparative transformer-based model, FT-Transformer, and using only one-hundredth of the number of parameters compared to complex SSL models such as SAINT. This study presents a highly effective and computationally efficient paradigm for learning tabular representations in label-deficient industrial environments. The code is available at https://github.com/yongeun-jang/GATE.
- 10 June 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 14, 90319-90333
Open AccessA Gated Attention-Based Semi-Supervised Learning Framework for Label-Scarce Tabular Data
Tabular data is a data format commonly used in various industries, including finance, medical services, and manufacturing. However, deep learning research for this data type has lagged behind the progress seen in computer vision and natural language processing. Real-world applications often face severe label scarcity due to high labeling costs. Traditional Gradient Boosting Decision Trees (GBDTs) and existing deep learning architectures struggle to achieve high predictive performance under these constraints. This study proposes the Gated Attention Tabular Encoder (GATE) and a two-stage semi-supervised learning pipeline. GATE effectively captures complex feature interactions by using global context from self-attention to dynamically regulate the flow of feature information. The proposed pipeline uses a teacher-student self-distillation framework to extract robust representations from unlabeled data. Then, it employs SoftNCA-based metric learning alongside high-confidence pseudo-labeling to optimize the embedding space with minimal labeled instances. Experimental results on public benchmark data showed that the proposed framework consistently achieved superior average performance across all label-ratio scenarios. The framework achieved an average accuracy of 62.23% with only 1% of the labeled data. It also achieved the highest average accuracy of 89.26% in a fully supervised setting, confirming its universal competitiveness. Through additional experiments, we confirmed that the proposed pipeline constructs a structurally superior representation space and achieves greater class separation compared to supervised learning models. In addition, in terms of computational efficiency, the proposed pipeline achieved this performance by using only 50% of the training parameters and 33% of the FLOPs compared to the comparative transformer-based model, FT-Transformer, and using only one-hundredth of the number of parameters compared to complex SSL models such as SAINT. This study presents a highly effective and computationally efficient paradigm for learning tabular representations in label-deficient industrial environments. The code is available at https://github.com/yongeun-jang/GATE.
- 29 March 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Device and Materials Reliability
- Vol. 22 (2) , 248-257
Fundamentals of Circuit Failure Analysis Based on Optical Fault Isolation Techniques
Circuit failure analysis based on optical fault isolation (OFI) techniques is widely used for Si debugging at the early phase of product development or failure analysis to improve yield and reliability issues at mass production stage. Three of OFI techniques are usually used for failure analysis. Dynamic laser stimulation affects Vth shift due to thermal heating or electron-hole pair generation in local area depending on the wavelength of the laser used. Laser voltage image and probing provide toggle image of signal and direct waveform differences between good and failure circuits, respectively. This paper introduces the fundamentals of Si level circuit analysis including digital and analog circuit using optical fault isolation method based on theoretical and experimental results.
- 29 March 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Device and Materials Reliability
- Vol. 22 (2) , 248-257
Fundamentals of Circuit Failure Analysis Based on Optical Fault Isolation Techniques
Circuit failure analysis based on optical fault isolation (OFI) techniques is widely used for Si debugging at the early phase of product development or failure analysis to improve yield and reliability issues at mass production stage. Three of OFI techniques are usually used for failure analysis. Dynamic laser stimulation affects Vth shift due to thermal heating or electron-hole pair generation in local area depending on the wavelength of the laser used. Laser voltage image and probing provide toggle image of signal and direct waveform differences between good and failure circuits, respectively. This paper introduces the fundamentals of Si level circuit analysis including digital and analog circuit using optical fault isolation method based on theoretical and experimental results.
- Open Access
- 1 February 2018
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 54 (4) , 213-215
0.00035 mm 2 on‐chip leakage sensing unit for various devices in 10 nm FinFET process
An efficient on‐chip leakage sensing unit is proposed, which is composed of four stages. Device under test (DUT) arrays include 16 types of transistors for leakage measurement. Threshold detector monitors the crossing point of inverter threshold causing the transition. Transition time is inversely proportional to the leakage current of the selected DUT. This time information of threshold detector is converted to voltage manner through the time‐to‐voltage converter with the diode stacked voltage generator. The generated voltage is transferred to voltage controlled oscillator (VCO) for frequency conversion which is the final output of leakage sensor. The proposed sensor provides leakage information of the various types of devices by using the same sub‐circuit within on‐chip. The prototype sensor occupies 0.00035 mm 2 area and consumes 1200 μW with eight DUT arrays within a chip. Experimental results show the well‐correlated frequency output with device leakage current.
- 1 February 2018
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 54 (4) , 213-215
Open Access0.00035 mm 2 on‐chip leakage sensing unit for various devices in 10 nm FinFET process
An efficient on‐chip leakage sensing unit is proposed, which is composed of four stages. Device under test (DUT) arrays include 16 types of transistors for leakage measurement. Threshold detector monitors the crossing point of inverter threshold causing the transition. Transition time is inversely proportional to the leakage current of the selected DUT. This time information of threshold detector is converted to voltage manner through the time‐to‐voltage converter with the diode stacked voltage generator. The generated voltage is transferred to voltage controlled oscillator (VCO) for frequency conversion which is the final output of leakage sensor. The proposed sensor provides leakage information of the various types of devices by using the same sub‐circuit within on‐chip. The prototype sensor occupies 0.00035 mm 2 area and consumes 1200 μW with eight DUT arrays within a chip. Experimental results show the well‐correlated frequency output with device leakage current.