S. M. A. Motakabber

Bangladesh faces three interlocking water quality crises: naturally occurring arsenic in shallow groundwater, salinity intrusion across the coastal southwest, and severe industrial and domestic pollution of the rivers around Dhaka. Conventional monitoring is too sparse, slow, and costly to manage these problems at national scale. This paper critically reviews how artificial intelligence (AI), and machine learning (ML) in particular, is being used to assess and improve water quality in the specific hydrological, climatic, and institutional context of Bangladesh, and asks what is still missing. We synthesise recent studies on arsenic risk mapping, coastal salinity forecasting, river water-quality-index (WQI) prediction, satellite and Internet-of-Things monitoring, and treatment optimisation, and summarise the governing equations of the dominant methods: tree ensembles, recurrent and physics-informed neural networks, and explainable AI. Reported performance commonly exceeds 0.9 (R²) for WQI regression and 0.9 accuracy for arsenic classification, yet most studies remain single-problem, single-region, and weakly validated across the monsoon cycle. We argue that the decisive gap is integration, and propose a national framework linking Bangladesh's monitoring agencies, remote sensing, and low-cost sensors to interpretable models and concrete management actions. We critically examine the principal barriers (data scarcity, seasonality, transferability, interpretability, and deployment capacity) and offer a prioritised research and policy roadmap aligned with Sustainable Development Goal 6. The contribution is a Bangladesh-specific synthesis and an actionable, interpretability-centred roadmap.

Brushless DC (BLDC) motors are now the dominant propulsion choice for electric vehicles (EVs) because of their high torque density, efficiency and reliability, but their nonlinear dynamics, electronic commutation, and wide load and speed range make fixed-gain control difficult. A single set of proportional–integral–derivative (PID) gains tuned at one operating point degrades when inertia, back-EMF, or load torque change. This paper presents a hybrid adaptive PID speed controller for a BLDC EV drive that couples an online PID auto-tuner that re-estimates the gains from a frequency response estimate of the plant, with a fast fixed-structure PID that supplies the rapid corrective action that the auto-tuner cannot provide during its estimation interval. The novelty of this work is this explicit two-element decomposition operating on a cascaded speed/voltage loop driven by Hall sensor feedback, which removes the need for an exact analytical feedback model while retaining the transparency of classical PID. A full analytical model of the BLDC machine and the closed-loop transfer functions is derived and implemented in MATLAB/Simulink. Across step references of 1000–1800 rpm and load steps to 10 N·m, and against a conventional fixed-gain PID and a Flower Pollination Algorithm (FPA)-tuned PID, the proposed controller holds overshoot below 1% at low-to-mid speed and a consistently lower torque ripple, while a 12.4% transient undershoot at 1800 rpm under sudden load identifies the present operating limit and a direction for future work.

Brushless DC (BLDC) motors are now the dominant propulsion choice for electric vehicles (EVs) because of their high torque density, efficiency and reliability, but their nonlinear dynamics, electronic commutation and wide load and speed range make fixed-gain control difficult. A single set of proportional–integral–derivative (PID) gains tuned at one operating point degrades when inertia, back-EMF or load torque change. This paper presents a hybrid adaptive PID speed controller for a BLDC EV drive that couples an online PID auto-tuner, which re-estimates the gains from a frequency-response estimate of the plant, with a fast fixed-structure PID that supplies the rapid corrective action the auto-tuner cannot provide during its estimation interval. The novelty of the work is this explicit two-element decomposition operating on a cascaded speed/voltage loop driven by Hall-sensor feedback, which removes the need for an exact analytical feedback model while retaining the transparency of classical PID. A full analytical model of the BLDC machine and the closed-loop transfer functions is derived and implemented in MATLAB/Simulink. Across step references of 1000–1800 rpm and load steps to 10 N·m, and against a conventional fixed-gain PID and a Flower Pollination Algorithm (FPA) tuned PID, the proposed controller holds overshoot below 1% at low-to-mid speed and consistently lower torque ripple, while a 12.4% transient undershoot at 1800 rpm under sudden load identifies the present operating limit and a direction for future work.

The scarcity of the spectrum is one of the key impediments to the growth of Internet of Things (IoT) applications and services. Cognitive Radio-based IoT (CR-IoT) is an advanced IoT framework in which the IoT integrates cognitive radio (CR) technology for dynamic spectrum sensing to mitigate spectrum scarcity and enhance wireless communication. CR-IoT is useful in diverse applications and sectors, such as healthcare, industrial IoT, smart cities, smart agriculture, military, and defense. The CR-IoT can use an IEEE 802.22-compliant Wireless Regional Area Network (WRAN) for backhaul and wide-area connectivity. In this paper, we propose an IEEE 802.22-compliant scheme called Efficient Spectrum Allocation (ESA) for CR-IoT networks. This study includes three novel algorithms for the ESA to distribute channels efficiently to primary and secondary users. The system model, spectrum accessibility along with priority, and channel access mechanisms for primary and secondary users are mathematically and graphically shown. The complexity and performance of the algorithms are evaluated using mathematical modeling and simulations. Simulation results show that the ESA significantly improves the overall performance parameters of CR-IoT in terms of throughput (3.5%–21%), spectrum utilization (7.5%–31%), collision reduction (up to 32%), and successful packet transmission (up to 21%) over the state-of-the-art.

Electric vehicles (EVs) must be used as the primary mode of transportation as part of the gradual transition to more environmentally friendly clean energy technology and cleaner power sources. Vehicle-to-grid (V2G) technology has the potential to improve electricity demand, control load variability, and improve the sustainability of smart grids. The operation and principles of V2G and its varieties, the present classifications and types of EVs sold on the market, applicable policies for V2G and business strategy, implementation challenges, and current problem-solving techniques have not been thoroughly examined. This paper exposes the research gap in the V2G area and more accurately portrays the present difficulties and future potential in V2G deployment globally. The investigation starts by discussing the advantages of the V2G system and the necessary regulations and commercial representations implemented in the last decade, followed by a description of the V2G technology, charging communication standards, issues related to V2G and EV batteries, and potential solutions. A few major issues were brought to light by this investigation, including the lack of a transparent business model for V2G, the absence of stakeholder involvement and government subsidies, the excessive strain that V2G places on EV batteries, the lack of adequate bidirectional charging and standards, the introduction of harmonic voltage and current into the grid, and the potential for unethical and unscheduled V2G practices. The results of recent studies and publications from international organizations were altered to offer potential answers to these research constraints and, in some cases, to highlight the need for further investigation. V2G holds enormous potential, but the plan first needs a lot of financing, teamwork, and technological development.

This paper discusses the challenges in developing a high-efficiency driver circuit for an ultrasonic cleaning system. The main issue lies in finding the suitable driver circuit and drive signal to ensure the correct frequency level for the ultrasonic transducer. This difficulty affects the removal of contaminants from inaccessible areas due to the inability to control cavitation bubbles. To address these problems, the authors studied the behaviour of piezoelectric transducers and designed driver and output power circuits. The LTspice XVII software was used to design and simulate various circuits, and it was found that trapezoidal pulses were the most suitable drive signals for avoiding power loss and achieving reasonable efficiency. The generated output frequency of 38.6 kHz provides sufficient energy for cleaning various small metallic items like jewellery, wristwatches, glasses, etc. The findings of this study will be helpful for those conducting research in this area in the future.

Magnetic Levitation Systems (MLS), or Maglev for short, utilise magnetic fields to levitate objects. They find applications in various scientific fields, particularly transportation, materials science, and biomedical engineering. Due to the diverse applications, different modelling and control approaches are necessary. The operation of each Maglev system depends on specific physical parameters. These key variables include the weight of the object being levitated, the current supplied to the system, the internal resistance and inductance of the electromagnet, and the distance between the object and the electromagnet. This research aims to understand the working principles of MLS. We will design and simulate a model based on real MLS hardware using MATLAB & Simulink. Additionally, we will create a functional Maglev prototype and program its control system using Arduino IDE and an Arduino microcontroller. MATLAB & Simulink offer a powerful tool for creating behavioral models for MLS. This model will then be integrated with Arduino programming to control the Maglev prototype.

This paper presents the development of a multi-AMBA system processor interface employing multiple AMBA processors. The primary goal of this interface is to establish connections between various AMBA AHB interfaces and external memory units such as RAM and REGISTER, leveraging the high-performance capabilities of AMBA AHB. The research delves into the utilization of ASICs to integrate processors and functional blocks into a System-On-Chip (SoC) configuration, enabling the execution of intricate applications. Within the ASIC environment, the research explores how processors communicate with their designated targets through an interface that standardizes the communication protocol for all targets. It underscores the challenges posed by data throughput and inter-processor/RTL communication in contemporary processors and suggests the concurrent use of multiple AMBA processors for accessing their respective targets. Additionally, the paper introduces an arbitration system for managing multiprocessor access and investigates the optimization of bulk data access while prioritizing crucial ASIC design constraints, including speed, low power consumption, and efficient area utilization. The proposed system was rigorously validated through simulation using Verilog HDL, yielding positive and promising results. ABSTRAK:  Kajian ini adalah mengenai pembangunan antara muka, sistem pemproses berbilang AMBA yang mengandungi berbilang pemproses AMBA. Tujuan antara muka ini adalah bagi mewujudkan hubungan pelbagai antara muka AMBA AHB dengan unit memori luaran seperti RAM dan REGISTER, ini sekaligus memanfaatkan keupayaan tinggi AMBA AHB. Kajian ini mengguna pakai ASIC bagi menyatukan pemproses dan blok berfungsi pada konfigurasi Sistem-Atas-Cip (SoC), membolehkan pelaksanaan aplikasi rumit. Pada persekitaran ASIC, kajian ini meneroka cara pemproses berkomunikasi dengan sasaran yang ditetapkan melalui perantaraan antara muka yang menyeragam protokol komunikasi bagi semua sasaran. Ia menggariskan cabaran yang ditimbulkan oleh pemprosesan data dan komunikasi antara pemproses/RTL dalam pemproses kontemporari dan mencadang penggunaan secara serentak pemproses berbilang AMBA bagi mengakses sasaran masing-masing. Selain itu, kertas kerja ini memperkenalkan sistem timbang tara bagi mengurus akses berbilang pemproses dan mengkaji akses data pukal yang optimum sambil mengutamakan kekangan reka bentuk ASIC, seperti kelajuan, penggunaan kuasa rendah dan penggunaan kawasan secara cekap. Sistem ini telah disahkan dengan teliti melalui simulasi menggunakan Verilog HDL, memberikan dapatan positif dan harapan baik.

DC-DC converters with significant gain, ripple-free input current, and shared ground are required to elevate the output voltages of batteries, fuel cells, and Photovoltaic sources. The proposed topology utilizes a solitary switch to control the circuit and it has additional inculpation of a voltage doubler cell at the load side, a switch capacitor cell in the middle, and a quadratic cell at the output side. These cascaded configurations lead to significant voltage gains at moderate duty cycle rates. Additionally, the voltage stress over the power components is negligible, coming in under one-third of the resultant voltage. Moreover, the number of cells at the input and output side can be extended to obtain high voltage according to the requirements of the load. The gain in voltage, efficiency, and normalized voltage stress of the semiconductor elements in the circuit are examined concerning other solutions found in the literature. Eventually, photovoltaic and battery sources were included to analyze the proposed topology to confirm the circuit’s multifaceted functionality. The circuit was developed for 270 W, 440 V output from 36 V input, and a 40 kHz switching pulse was used to drive the switch. The theoretical and simulation analysis states that incorporating photovoltaic and other sources did not deteriorate the transformation efficiency. Simulink and PSIM analysis found that the circuit successfully transferred power from source to load. ABSTRAK: Penukar DC-DC yang mempunyai gandaan ketara, input arus bebas riak dan pembumi berkongsi penting bagi meningkatkan voltan keluar bateri, sel bahan api dan sumber fotovolta. Topologi yang dicadangkan ini menggunakan suis tersendiri bagi mengawal litar dan ia mengandungi sel pendua voltan tambahan bagi menghentikan arus di bahagian beban, sel suis kapasitor di tengah dan sel kuadratik di bahagian voltan keluar. Konfigurasi berturutan ini membawa kepada gandaan voltan ketara pada kadar kitar tugas sederhana. Tambahan, tekanan voltan ke atas komponen kuasa boleh diabaikan, iaitu satu pertiga daripada voltan terhasil. Selain itu, bilangan sel di bahagian kemasukan dan keluaran arus boleh dilanjutkan bagi mendapatkan voltan tinggi mengikut keperluan beban. Gandaan voltan, kecekapan dan tekanan voltan ternormal pada bahan dalam litar semikonduktor diperiksa dengan menyamai penyelesaian lain yang ditemui dalam kajian terdahulu. Akhirnya, sumber fotovolta dan bateri dimasukkan bagi menganalisis topologi yang dicadangkan bagi mengesahkan fungsi pelbagai rupa litar. Litar yang dibangunkan ini digunakan pada kuasa 270 W, pada aras voltan 440 V dengan kemasukan voltan 36 V dan suis operasi berfrekuensi 40 kHz. Analisis teori dan simulasi menyatakan bahawa gabungan fotovolta dan sumber lain tidak mengurangkan kecekapan transformasi. Analisis Simulink dan PSIM mendapati litar ini berjaya memindahkan 95% kuasa dari sumber kepada beban.