Wei Wei

The CEPC clock issue is related with the RF frequency coordination between the various accelerator systems and may affect the operation modes of both the accelerator and the detector. The timing structure of CEPC has been restudied with the collaboration of the accelerator team and the detector team. After discussions between two sides, the CEPC bunch structure is set such that the spacings between adjacent bunches in any CEPC operation mode are integer numbers of 23.08[Formula: see text]ns. The master CEPC clock will be provided by the accelerator to the detector systems with a frequency of 43.33[Formula: see text]MHz, synchronous to the beam. The CEPC detector system relies on the clock to sample physics signal at the right time. It was found that if the circumference of CEPC is slightly changed to 99955.42[Formula: see text]m, the detector would benefit more for the first 10-year operation.

The Circular Electron-Positron Collider (CEPC), as the next-generation electron-positron collider, is tasked with advancing not only Higgs physics but also the discovery of new physics. Achieving these goals requires high-precision measurements of particles. Taichu seires, Monolithic Active Pixel Sensor (MAPS), a key component of the vertex detector for CEPC was designed to meet the CEPC's requirements. For the geometry of vertex detector is long barrel with no endcap, and current silicon lacks a complete digitization model, precise estimation of cluster size particularly causing by particle with large incident angle is needed. Testbeam results were conducted at the Beijing Synchrotron Radiation Facility (BSRF) to evaluate cluster size dependence on different incident angles and threshold settings. Experimental results confirmed that cluster size increases with incident angle. Simulations using the Allpix$^2$ framework replicated experimental trends at small angles but exhibited discrepancies at large angles, suggesting limitations in linear electric field assumptions and sensor thickness approximations. The results from both testbeam and simulations have provided insights into the performance of the TaichuPix chip at large incident angles, offering a crucial foundation for the establishment of a digital model and addressing the estimation of cluster size in the forward region of the long barrel. Furthermore, it offers valuable references for future iterations of TaichuPix, the development of digital models, and the simulation and estimation of the vertex detector's performance.

The TaichuPix chip, designed as a dedicated monolithic active pixel sensor for CEPC vertex detector R&D, requires a raw data rate of up to 3.84 Gbps and a power consumption of less than 25 mA/Gbps for the serializer circuit. The initial prototype TaichuPix1 achieved a maximum data rate of 3.36 Gbps but exhibited significant jitter and current issues. Subsequently, two 4-Gbps serializers were developed and optimized to meet the specified requirements. Despite encountering a bias issue initially, test results demonstrate that the root mean square (RMS) jitter of both phase-locked loop (PLL) clocks is less than 1.8 ps. A revision was implemented to address the bias problem by utilizing simple diode-connected transistors to provide the reference current. Tests conducted revealed a clear eye diagram at 4 Gbps, with a total jitter of 62.1 ps, power consumption of 151.2 mW, and the RMS jitter of the ROPLL less than 1.4 ps.

Shanghai HIgh repetition rate XFEL aNd Extreme light facility (SHINE) is a free electron laser facility with a high pulse repetition rate of up to 1 MHz. STARLIGHT (SemiconducTor Array detectoR with Large dynamIc ranGe and cHarge inTegrating readout) is a pixel array detector with a high frame rate (≥ 10 kHz) and a large dynamic range (up to 10⁴ photons of 12.4 keV), which is being developed for SHINE. The readout ASIC utilized by STARLIGHT in the front-end module is HYLITE (High dYmamic range free electron Laser Imaging deTEctor). HYLITE200F with 200 μm × 200 μm pixel size and 64 × 64 pixels is the first full-scale chip of the HYLITE series. To facilitate the improvement of the detector, the performances of the single chip and a detector prototype module with 2 × 2 ASICs are carefully evaluated, especially in terms of gain, noise, and dynamic range. The test results show that the gains of the HYLITE200F chip are uniform with a single-photon resolution. Meanwhile, the chip maintains a good linearity at 10⁴ photons of 12 keV. After bump-bonding with the sensor, the performance of HYLITE200F still fulfills the requirements.

HYLITE (High dYmamic range free electron Laser Imaging deTEctor) is a charge-integration detector readout chip designed for SHINE (Shanghai HIgh repetition rate XFEL aNd Extreme light facility), featuring a dynamic range of 10000 photons at 12 keV, a resolution of a single photon, and a high frame rate aiming for 10 kHz. HYLITE200F is the first full-scale chip of HYLITE manufactured in a 130 nm CMOS process. The engineering-run chip consists of 64 × 64 pixels with a pixel pitch of 200 μm. As the first step of the project, the HYLITE200F chip works at a frame rate of 1 kHz in a successive mode. To deal with the power supply issue and a high data rate, the layout of the pixel array and the clock distribution structure is carefully designed. Furthermore, prototype front-end modules were manufactured to verify the function of sensors, ASICs, and the reliability of the bump-bonding process. Test results show that HYLITE200F can work steadily at a frame rate of 1 kHz.

The High Energy Photon Source (HEPS) represents a fourth-generation light source. This facility has made unprecedented advancements in accelerator technology, necessitating the development of new detectors to satisfy physical requirements such as single-photon resolution, large dynamic range, and high frame rates. Since 2016, the Institute of High Energy Physics has introduced the first user-experimental hybrid pixel detector, progressing to the fourth-generation million-pixel detector designed for challenging conditions, with the dual-threshold single-photon detector HEPS-Beijing PIXel (HEPS-BPIX) set as the next-generation target. HEPS-BPIX will employ the entirely new Application-Specific Integrated Circuit (ASIC) BP40 for pixel information readout. Data flow will be managed and controlled through readout electronics based on a two-tier Field-Programmable Gate Array (FPGA) system: the Front-End Electronics (FEE) and the Input-Output Board (IOB) handle the fan-out for 12 ASICs, and the μ4FCP is tasked with processing serial data on high-speed links, transferring pixel-level data to the back-end RTM and μTCA chassis, or independently outputting through a network port, enabling remote control of the entire detector. The new HEPS-BPIX firmware has undergone a comprehensive redesign and update to meet the electronic characteristics of the new chip and to improve the overall performance of the detector. We provide an overview of the core subunits of HEPS-BPIX, emphasizing the readout system, evaluating the new hardware and firmware, and highlighting some of its innovative features and characteristics.

The Circular Electron Positron Collider (CEPC) has been proposed to enable more thorough and precise measurements of the properties of Higgs, W, and Z bosons, as well as to search for new physics. In response to the stringent performance requirements of the vertex detector for the CEPC, a baseline vertex detector prototype was tested and characterized for the first time using a 6 GeV electron beam at DESY II Test Beam Line 21. The baseline vertex detector prototype is designed with a cylindrical barrel structure that contains six double-sided detector modules (ladders). Each side of the ladder includes TaichuPix-3 sensors based on Monolithic Active Pixel Sensor (MAPS) technology, a flexible printed circuit, and a carbon fiber support structure. Additionally, the readout electronics and the Data Acquisition system were also examined during this beam test. The performance of the prototype was evaluated using an electron beam that passed through six ladders in a perpendicular direction. The offline data analysis indicates a spatial resolution of about 5 um, with detection efficiency exceeding 99 % and an impact parameter resolution of about 5.1 um. These promising results from this baseline vertex detector prototype mark a significant step toward realizing the optimal vertex detector for the CEPC.

HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel readout chip designed for SHINE (Shanghai HIgh repetition rate XFEL aNd Extreme light facility). The target specifications for the full-size HYLITE chip include a pixel matrix of 128 × 128 pixels and a frame rate of 10 kHz. In order to meet these specifications, two small-scale chips, designated HYLITE0.1 and HYLITE0.2, were fabricated and underwent comprehensive testing. Some issues were discovered during tests including the noise performance and the error of output ADU (Analog Digital Units) codes. The HYLITE200S represents the third prototype chip developed to address the above issues. The CDS (Correlated Double Sampling) circuits and glitch-clear clock structures are integrated in pixels. Furthermore, to meet the data output rate requirements of the full-size chip, a high-speed data interface has been designed. Test results show that the signal-to-noise ratio is improved to 9.31 for a 12 keV single photon, and the ADU error is fixed. By integrating a phase-locked loop and a balanced encoding logic, the data interface can work steadily at a speed of 3.125 Gbps.