Jinwang Zhang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Jinwang Zhang has a total of 6 co-authors. Here are the top co-authors by number of shared publications:
- Fangxu Lv
School of Computer, National University of Defense Technology, Changsha 410003, China
2 shared publications - Jianjun Shi
School of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, China
2 shared publications - Zixiang Tang
School of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, China
2 shared publications - Dongbin Lv
School of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, China
1 shared publication - Jiahang Wei
School of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, China
1 shared publication - Xinjie Wang
School of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, China
1 shared publication
Latest Publications
- Open Access
- 9 October 2022
- Published by MDPI AG in Electronics
- Vol. 11 (19) , 3246
A High Phase Detection Density and Low Space Complexity Mueller-Muller Phase Detector for DB PAM-4 Wireline Receiver
A Mueller-Muller Phase Detector (MM PD) technology based on duo-binary four-level pulse amplitude modulation (DB PAM-4) with low complexity and high phase-detection density is presented. The proposed low complexity includes low phase-detection complexity and low space complexity of data processing. The waveform sifting technology simplifies 175 specific waveform changes into five fuzzy waveform change trends, reducing the complexity of subsequent phase detection. By making the data sample before the waveform sifting, the data bit width is reduced from 8 bit to 3 bit, which realizes data dimensionality reduction, greatly reduces the scale of subsequent auxiliary data, reduces the number of basic devices by 13.7%, and reduces the spatial complexity of data processing. The coherent coding of DB PAM-4 combined with waveform sifting increases the phase-detection density from 50% to 65% and improves both phase-detection density and phase-detection gain by 30%, and improves the jitter tolerance. Through the simulation of the clock and data recovery (CDR) model built by Cadence, the fast locking capability of CDR is verified.
- 9 October 2022
- Published by MDPI AG in Electronics
- Vol. 11 (19) , 3246
Open AccessA High Phase Detection Density and Low Space Complexity Mueller-Muller Phase Detector for DB PAM-4 Wireline Receiver
A Mueller-Muller Phase Detector (MM PD) technology based on duo-binary four-level pulse amplitude modulation (DB PAM-4) with low complexity and high phase-detection density is presented. The proposed low complexity includes low phase-detection complexity and low space complexity of data processing. The waveform sifting technology simplifies 175 specific waveform changes into five fuzzy waveform change trends, reducing the complexity of subsequent phase detection. By making the data sample before the waveform sifting, the data bit width is reduced from 8 bit to 3 bit, which realizes data dimensionality reduction, greatly reduces the scale of subsequent auxiliary data, reduces the number of basic devices by 13.7%, and reduces the spatial complexity of data processing. The coherent coding of DB PAM-4 combined with waveform sifting increases the phase-detection density from 50% to 65% and improves both phase-detection density and phase-detection gain by 30%, and improves the jitter tolerance. Through the simulation of the clock and data recovery (CDR) model built by Cadence, the fast locking capability of CDR is verified.
- Open Access
- 10 August 2022
- Published by MDPI AG in Electronics
- Vol. 11 (16) , 2486
A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS
To reduce the high bit error rate of serial transceivers under strong channel attenuation, a low-power 112 Gb/s SerDes transmitter was designed using a duo-binary PAM4 modulation technology. By adopting duo-binary PAM4 modulation technology, the problem of the low bandwidth utilization of a high-speed PAM4 (pulse amplitude modulation 4) signal was improved. The problem of high jitter caused by charge sharing and the limited bandwidth of a 4:1 high-speed MUX was improved by using precharging auxiliary transistors. The system power consumption of the transmitter was reduced by using a 7-bit weighted voltage-driven digital-to-analog converter (DAC). The transmitter was designed with a 28 nm CMOS process and powered by a voltage of 0.9 V. The simulation results showed that when the channel attenuation was 20.9 dB, the transmitter could work at 112 Gb/s, the power consumption was 2.02 pJ/bit, and the linearity was 96.7%.
- 10 August 2022
- Published by MDPI AG in Electronics
- Vol. 11 (16) , 2486
Open AccessA 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS
To reduce the high bit error rate of serial transceivers under strong channel attenuation, a low-power 112 Gb/s SerDes transmitter was designed using a duo-binary PAM4 modulation technology. By adopting duo-binary PAM4 modulation technology, the problem of the low bandwidth utilization of a high-speed PAM4 (pulse amplitude modulation 4) signal was improved. The problem of high jitter caused by charge sharing and the limited bandwidth of a 4:1 high-speed MUX was improved by using precharging auxiliary transistors. The system power consumption of the transmitter was reduced by using a 7-bit weighted voltage-driven digital-to-analog converter (DAC). The transmitter was designed with a 28 nm CMOS process and powered by a voltage of 0.9 V. The simulation results showed that when the channel attenuation was 20.9 dB, the transmitter could work at 112 Gb/s, the power consumption was 2.02 pJ/bit, and the linearity was 96.7%.