Xiqin Tang

A high-accuracy approximate multiplier design method for artificial intelligence applications is presented in this paper. By analyzing the real operand distributions observed in CNN inference, we show that partial-product arrays exhibit pronounced sparsity under practical workloads. Based on this observation, a sparse-dense separation circuit is introduced to reconstruct partial products, and a family of approximate compressors with only negative errors is developed. A reconfigurable two-stage hybrid compression tree is then proposed to build several high-accuracy 8-bit approximate multipliers. Hardware synthesis and application-level evaluations demonstrate that the proposed designs achieve Pareto-optimal accuracy–energy trade-offs under both uniform inputs and real non-uniform CNN operands. In the SMIC 55 nm process, the proposed multipliers reduce area and power by more than 62.28% and 55.23% respectively compared with the exact multiplier. In image multiplication,they achieve a structural similarity index (SSIM) higher than 99.95% and a peak signal-to-noise ratio (PSNR) exceeding 57 dB. In ResNet-18/ImageNet inference, the Top-1 accuracy loss is limited to 0.09% ∼ 0.11%.

In this paper, two approximate Radix-4 Booth encoders AR4BE1 and AR4BE2 (Approximate Radix-4 Booth Encoder1, 2) are proposed to achieve great accuracy-cost trade-off, and a series of signed approximation multipliers (SAMs) are designed based on a hybrid coding approach, where the most significant bits (MSB) use exact radix-4 encoder, and the least significant bits (LSB) use the proposed AR4BE1 and AR4BE2. And a simple error compensation circuit is used to reduce the accuracy loss in partial product array reduction. The proposed SAMs can be reconfigured for different applications with different accuracy-cost trade-off requirement. We comprehensively evaluate the SAMs with respect to both hardware implementation and error analysis. Compared to the exact multiplier, the highest accuracy multiplier H10M6L0, has 22.8%, 32.1%, and 18.4% reduction in area, power consumption, and delay, respectively. The case study for image edge detection also proves the validity of the proposed SAMs in error-tolerant application.

The sparsity of spike generation in neuromorphic computing establishes asynchronous communication as inherently more suited than SERializer/DESerializer (SerDes) for handling sparse inter-chip transmissions. However, traditional asynchronous methods often require more wires than the data bit width due to data encoding schemes. This paper introduces a novel method, Detecting Data Stable Receiver-Transmitter (D2SRT), for inter-chip communication in neuromorphic chips. By detecting data stability, D2SRT achieves low power and high performance, with a single-bit energy consumption of 13.9pJ and throughput of 217.2Mbps, surpassing traditional methods. Experimental results show that D2SRT meets the bandwidth requirements for most Spiking Neural Networks (SNNs) and achieves exceptionally low dynamic power consumption.

This paper presents a high-performance and synthesizable asynchronous pipeline called HPSAP pipeline. First, a 4-phase pipeline controlled by the relative-timing (RT) controller is designed. The controller is small (7 gates) and its handshake protocol is highly concurrent, resulting in fewer component delays in cycle time. However, the RT pipeline’s throughput is limited by the inherent reset phase in the 4-phase protocol. Thus, the variant HPSAP pipeline is proposed with the quasi-2phase conversion method. Unlike other existing solutions which aimed at reducing the reset time of the 4-phase protocol, this method imitates the behavior of the 2-phase pipeline and re-activates the reset edge by two steps: 1) replacing all delay-matched units with the maximum delay; 2) adding a small pulse generator on each RT controller. The post-layout HSPICE simulation of a 4-bit 10-stage HPSAP FIFO indicated a throughput of 5.382 giga data item per second (GDI/s) under SMIC 55nm CMOS technology, which was 77.5% and 14.65% higher than the Click pipeline and Mousetrap pipeline. In the pipeline with processing, a 32×32 bits multiplier was built, and the maximum working frequency of the HPSAP multiplier was faster than Mousetrap and the synchronous counterparts.

In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. The comparison results prove that the IVS multiplier reduces at least 61.9% of the area and 45.18% of the power over its counterparts. To increase the hardware resource utilization, a Transverse Carry Array (TCA) structure for Partial Products Accumulation (PPA) was designed by replacing the 32-bit adders with 3/17-bit adders in the 16-bit multipliers. The experiment results show that the optimization could lead to at least a 6.32% and 13.65% reduction in power consumption and area cost, respectively, compared to the standard 16-bit radix-8 Booth multiplier. In the end, the precise scale of the proposed IVS multiplier is discussed. Benefiting from the modular design, the IVS multiplier can be configured to support sixteen different kinds of multiplications at a step of 16 bits [16b, 32b, 48b, 64b] × [16b, 32b, 48b, 64b].