Geng Zhang

With the growing demand for data center interconnect (DCI) capacity, partial response equalization (PRE), employing either a 1/(1+D) decoder or an maximum likelihood sequence estimation (MLSE) decoder, has emerged as an effective solution to address the critical bandwidth limitations restricting system transmission rates. However, the 1/(1+D) decoder suffers from its inherent feedback loop and error propagation, while the MLSE decoder is limited by its high hardware complexity. Meanwhile, blind adaptive algorithms also encounter bottlenecks in PRE. Severe bandwidth limitations significantly impact the blind convergence of the decision-directed least mean squares (DD-LMS) algorithm. Additionally, PRE adversely affect the traditional zero forcing (ZF) algorithm, leading to extended convergence times. In this paper, we propose and experimentally demonstrate a hardware implementable PRE with reduced-state sequence estimation (RSSE) decoder and delay-ZF algorithm in a real-time 80 Gbps four-level pulse amplitude modulation (PAM-4) intensity modulation/direct detection (IM/DD) transmission system based on an FPGA chip. Statistical results from various transmission scenarios indicate that the RSSE decoder achieves BER performance comparable to that of the full-state MLSE decoder, while reducing the implementation complexity by up to 75%. Moreover, experimental results demonstrate that under blind equalization, employing the delay-ZF algorithm to update the PAM-7 targeted FFE reduces the blind convergence time by up to 55.8% and 74.9% compared to the traditional ZF and DD-LMS algorithms, respectively.

This paper presents a symmetric correlated coding (SCC) scheme and the corresponding high-density transceiver that deliver 7-bit data over 8 lanes. The SCC method implements the 7-bit data encoding jointly in 8 correlated channels which improves the pin efficiency up to 87.5%. Besides, as an advanced chord signaling, the SCC exhibits the immunity to crosstalk, common-mode noise (CMN) and simultaneous switching noise (SSN). The proposed SCC transceiver innovates a SCC source-series-terminated (SST) driver that maintains an unchanged bandwidth even with a low-voltage power supply, and the CTLE decoder adopts the active inductor to compensate the channel loss. Prototyped in 28-nm CMOS, the proposed wireline transceiver using SCC method supports a maximum data rate of $7\times 10$ Gb/s with a bit error rate (BER) <1e−12, achieving a data rate density (DRD) up to 61.4 Gb/s/mm. The SCC transceiver dissipates 99.4 mW with the energy efficiency of 1.42 pJ/bit.

With the evolution of high-performance computer and data center interconnect communication rates from 53.125Gbps to 106.25Gbps, high-speed serial interfaces face a dramatic increase in BER challenges, which seriously affects interconnect performance and system stability. To address the challenge of high BER of 106.25Gbps PAM4 receiver, this paper proposes a cooperative adaptive equalizer structure, which adopts three equalizers and adaptive cooperative equalization algorithm to achieve low BER under large insertion loss conditions. In addition, a blind adaptive equalization algorithm based on judgment feedback equalizer is proposed to shorten the link training time. In this paper, a 12nm CMOS process is used to design a receiver based on cooperative adaptive equalizer. Simulation shows that the receiver with cooperative adaptive equalizer can support BER less than e-12 for a de-emphasized l06.25Gbps PAM4 signal after 34.3dB @ 26.5625G Hz channel, and the convergence period is less then 0.2 us.

This paper analyzes the performance requirements that need to be met by a clock generator applied to a low-temperature quantum computer and analyzes the negative effects on the clock generator circuit under low-temperature conditions. In order to meet the performance requirements proposed in this paper and suppress the negative effects brought about by the low temperature, a clock generator for ultra-low-temperature quantum computing is designed. This clock generator is designed by using F-CLASS Voltage Controlled Oscillator (VCO), power filter, tail resistor, differential charge pump, and other techniques. And the noise characteristics of the clock generator are analyzed by Impulse Sensitive Function (ISF) and simulation results. After simulation tests, the average power consumption of the clock generator designed in this paper is 7 mW, the phase noise is −121 dBc/Hz@1 MHz, and the jitter is 62 fs. The performance of the clock generator meets the performance requirements proposed in this paper, and the reduction in the corner frequency proves that the circuit will have better performance at low temperatures.

This paper proposes a frequency domain model for injection-locked LC oscillators by introducing the impulse sensitivity function (ISF) and injection factor, analyzes the effect of the injection pulse width and injection position on oscillator performance based on this model, and derives an equation that can guide the design and optimization of oscillators. The model fills the gap in the field of frequency domain models for injection-locked LC oscillators. Based on the above model, a clock generator circuit structure operating at 14 GHz, combining a phase-locked loop with an injection-locked oscillator, is designed and measured based on a 65-nm cmos process. The circuit achieves better phase noise performance by optimizing the two parameters, which verifies the accuracy of the proposed model.

A novel high-speed transceiver based on 7 bit correlated non-return-to-zero(CNRZ-7) with high-bandwidth-density(bandwidth per unit length) and low-power for Die-to-Die(D2D) communication is proposed. In order to further improve the SNR and the bandwidth of the CNRZ-5 in D2D communication, a CNRZ-7 based transmitter matrix and receiver matrix are proposed firstly, which are derived from Walsh Hadamard(W-H) transform and inverse transformation. In addition, to reduce the power consumption of the transmitter, the encoding driver based on CNRZ-7 transmitter matrix is designed with source series terminated drivers(SST). To further improve the SNR of the receiver, the decoding circuit based on CNRZ-7 receiver matrix is designed with a special multi-input comparators(MIC), which contain equalizer circuits. This transceiver is designed with a 28nm CMOS technology and the core area is 0.66mm2. The post-simulation results show that this transceiver can operate at 280 Gb/s, and the data rate is 35 Gb/s/wire. The worst width of the receiver’s eye-diagrams is 0.45UI when the transceiver operates at a 50 mm PCB channel with a 10dB@20GHz insertion loss, and the total BER is less than 1E-15. The power consumption is 1.1pJ/b under a normal corner.

The disasters may cause multiple fiber failures, resulting in serious network capacity loss. This makes it difficult to provide enough spectrum resources for the massive unexpectedly interrupted services recovery, which requires more efficient algorithm to make better use of the remaining resources to improve the survivability of the elastic optical network (EON). Since which service flow is recovered first has impact on the total recovery ratio, this paper proposed an ordering aware service recovery algorithm with routing modulation and spectrum assignment (OASR-RMSA), and used genetic operator to find an optimal service recovery order, so that the available spectrums can be fully used and more services can be accommodated. The simulation results show the proposed algorithm has 10% improvement in blocking probability(BP) than the benchmark algorithms, when there are multiple failures in the EON.