Florent Bouyjou

The proposed PRISME chip contains a new Phase-Locked Loop IP block for clock signal generation with a jitter lower than 10 ps and a radiation tolerance up to 300 Mrad. To be compatible with a large range of applications at the Electron-Ion Collider and at the Large Hadron Collider, it needs to accept a large input frequency range (80 MHz and 100 MHz), with output frequencies within 1.6–2 GHz. It is designed in TSMC 65 nm technology to allow its integration in future readout ASICs, such as the SALSA chip for readout of micro pattern gaseous detectors. Test results in agreement with simulations are well within the application requirements of the SALSA ASIC. The Phase-Locked Loop occupies an area of 0.07 mm ² and consumes 6.2 mA from a 1.2 V supply. The output jitter integrated from 5 kHz to 80 MHz is 1.26 ps rms for a frequency division ratio of 20.

The CMS High Granularity Calorimeter (HGCAL), developed for the High luminosity phase of the LHC (HL-LHC), uses custom ASICs — HGCROC3 and H2GCROC3 — to read out silicon sensors and SiPM-on-tile modules. These chips provide precise charge and timing measurements, digital processing for triggering, and are designed to operate in harsh radiation conditions. Version 3 of the chips implements all final features, with sub-versions a–d addressing bugs and improving radiation tolerance. Extensive testing has been performed in lab and beam environments. The proceedings covers chip design, performance, and SEE-related issues and fixes.

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. The final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

The ASIC EICROC is designed to read out the AC-LGAD detectors for the future EIC at Brookhaven National Laboratory (BNL). These detectors should combine excellent temporal (20–30 ps) and spatial (≈20 µm) resolution, enabling a new generation of pixel detectors with precise time measurement. Designing an ASIC to read out the AC-LGAD detectors represents a significant technological challenge. The EICROC ASIC measures and digitizes the charge and the Time-of-Arrival (ToA) with a resolution of 25 ps, transmitting these data to the back-end electronics. The first prototype, EICROC0, was submitted using CMOS 130 nm node in 2022.

This paper proposes and evaluates an architecture for a low-power Time-to-Digital Converter (TDC) with high resolution, optimized for high-rate operation (40MSa/channel), and integration with analog front-end in multichannel readout chips in 130 nm CMOS technology. The converter is based on a three-step architecture. The first step uses a counter and the following ones are based on two types of Delay-Line (DL) structures. A programmable Time Amplifier (TA) is used between the second and third steps to reach a final resolution of 24.4 ps in the standard mode of operation. In addition, this architecture uses common continuously stabilized master blocks that control the channels against the effects of global Process, Voltage, and Temperature (PVT) variations. We also propose a per-channel DL gain correction based on a trimmable block to correct mismatch effect. The area of the TDC channel is only 0.051 mm ² . For a 40MSa/channel rate, the TDC average power consumption measured per channel is 2.2 mW for a 100% hit occupancy and decreases to 311 μW for the 10% occupancy specified for our main application. The demonstrated compactness and low power consumption fully match our requirements for integration into multichannel front-end chips. The experimental results demonstrate good timing performance over a broad range of operating temperatures (-35°C and 65°C), which conforms to our expectations. For example, the measured timing integral nonlinearity is better than ±1 LSB (±25 ps), and the overall timing precision is better than 21 ps RMS.

This paper presents a 13-b, 2.56-μs conversion time, 2 V input range, 32-channel single slope analog-to-digital converter (ADC) called OWB-1 and implemented in a 0.35-μm CMOS commercial technology. It is based on an improved Wilkinson architecture. An interpolator composed by a delay lock loop is used to increase the time resolution of the counter by a factor of 32, while keeping a low power consumption and ensuring the high dynamic performance of the ADC. Measurements performed on the ADC have shown that the noise is better than 0.86 LSB over the full conversion range, its differential nonlinearity is in the range of -0.28/+0.31 LSB and its integral nonlinearity is within -1.3/+2.1 LSB. The total power consumption of the chip is 57 mW for 32 active channels. A new temperature compensation system based on a servo loop has also been integrated into the chip to compensate for temperature effects in the -40°C to +40°C range. Special design techniques have been used to make the ASIC immune to single event latchup. OWB-1 readout is optimized for a new low power microgamma camera (Caliste-MC2) with digital output based on a 32 x 32 CdTe or CdZnTe pixel matrix.

TARANIS (Tool for the Analysis of RAdiation from lightNIng and Sprites) is a microsatellite aimed to atmospheric storms study. It embarks among other instruments IDEE (Instrument Detecteur d'Electron Energetique) which is dedicated to energetic electron characterization in the range from 70keV to 4Mev. To cover such awide ran ge, two types of detectors are required: Silicon (Si) and Cadmium Telluride (CdTe) based detector for the 70keV to 700keV and for the 300keV to 4MeV respectively. Si detectors are placed in front of CdTe detectors for angle measurement. Although the readout architecture of both detectors are similar, the time constants involved in collection of the charges for Si and CdTe are differents by almost 21 decades (60ns for Si and 3f.1s for CdTe). Two different readout circuits are thus required. CdTe type channels need to make use of Pole Zero Cancellation (PZC) technique in order not to impede the frequency of operation. Performance of the design has been characterized on a test board as well as interfaced with detectors. Finally, results of its characterized Single Event Latchup (SEL) performance is given.