Kevin Skadron

Summary: CRISPR/Cas9 technology has revolutionized genome editing, but ensuring its safety requires genome-wide identification of all potential off-target sites (OTSs), defined as sites similar to the on-target site up to an edit-distance threshold. Existing computational methods can scan large genomes up to a given edit-distance threshold, but they face severe computational bottlenecks, including low throughput, sub-optimal CPU utilization, and memory exhaustion, when scaling to multiple guide RNAs (gRNAs) or to high edit distances. Here, we present AutoFFinder, a runtime-reconfigurable, hardware-software co-designed platform for multi-gRNA CRISPR/Cas9 OTS search. AutoFFinder combines a high-throughput Levenshtein automata FPGA overlay (ReLev), which streams genomic data to evaluate up to 128 gRNAs concurrently, with a parallel CPU stage that reconstructs exact alignments under versatile mismatch and bulge constraints. Importantly, ReLev supports runtime updates to both the gRNA sequences and the edit-distance threshold, allowing end users to use the platform without FPGA toolchain expertise and overcoming the rigidity of previous FPGA implementations, which required full hardware recompilation to change patterns or thresholds. Benchmarking on the human reference genome (hg38) showed that, for 128 gRNAs at an edit-distance threshold of 6, AutoFFinder completed an end-to-end search in 68.43 seconds (1.14 minutes), compared with 190.62 seconds (3.18 minutes) by a GPU-based Myers’ Bitparallel algorithm and 38.0–38.7 minutes by applicable state-of-the-art CPU-based methods. In addition, AutoFFinder is guaranteed to recover all potential OTSs as demonstrated in a separate completeness validation. In summary, AutoFFinder provides a highly scalable, FPGA-accelerated solution for rigorous CRISPR design workflows. Availability and implementation: The source code for AutoFFinder is publicly available at https://github.com/OrensteinLab/AutoFFinder. Supplementary information: is available on Bioinformatics online.

The disparity between processor speed and memory bandwidth has become a growing performance bottleneck, particularly for memory-intensive workloads. Processing-in-Memory (PIM) mitigates this bottleneck by integrating computation directly within DRAM. However, the effectiveness of PIM varies significantly across workloads, architectures, and DRAM technologies, yet it is often assessed using tightly coupled simulators and benchmarks that lack portability and generality. This article extends PIMbench and PIMeval —a generalizable benchmark suite and an extensible PIM simulator to support a broader range of workloads, PIM architectures, and DRAM technologies. This evaluation incorporates roofline analysis and a breakdown of intra-memory execution stages to identify PIM-specific bottlenecks and performance scaling limits. The evaluation spans three classes of digital PIM architectures: subarray-level bit-serial, subarray-level bit-parallel, and bank-level bit-parallel. It further demonstrates how internal DRAM parameters such as subarray count and GDL width impact PIM performance. The code is publicly available at: https://github.com/UVA-LavaLab/PIMeval-PIMbench .

The Last Level Cache (LLC) is the processor’s critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low operation energy. To date, high-density (HD) SRAM has been the conventional device of choice; however, with the slowing of transistor scaling, as reflected in the industry’s almost identical HD SRAM cell size from 5 nm to 3 nm, alternative solutions such as 3D stacking with advanced packaging (i.e., hybrid bonding) are pursued (as demonstrated in AMD’s V-cache). Escalating data demands necessitate ultra-large on-chip caches to decrease costly off-chip memory movement, pushing the exploration of device technology towards monolithic 3D (M3D) integration, where transistors can be stacked in the back-end-of-line (BEOL) at the interconnect level. M3D integration requires fabrication techniques compatible with a low thermal budget (<400°C). Among promising BEOL device candidates are amorphous oxide semiconductor (AOS) transistors, particularly desirable for their ultra-low leakage (seconds) when used in a gain-cell configuration. This paper examines device, circuit, and system-level tradeoffs made when optimizing BEOL-compatible AOS-based 2-transistor gain cells (2T-GC) for LLC. A cache early-exploration tool, NS-Cache, is developed to model caches in advanced 7 & 3 nm nodes and is integrated with the Gem5 simulator to systematically benchmark the impact of the newfound density/performance when compared to HD-SRAM, MRAM, and 1T1C eDRAM alternatives for LLC.

Bit-serial processing-in-memory (PIM) architectures have been extensively studied, yet a standardized tool for generating efficient bit-serial code is lacking, hindering fair comparisons. We present a fully automated compiler framework, PIMsynth, for bit-serial PIM architectures, targeting both digital and analog substrates. The compiler takes Verilog as input and generates optimized micro-operation code for programmable bit-serial PIM backends. Our flow integrates logic synthesis, optimization steps, instruction scheduling, and backend code generation into a unified toolchain. With the compiler, we provide a bit-serial compilation benchmark suite designed for efficient bit-serial code generation. To enable correctness and performance validation, we extend an existing PIM simulator to support compiler-generated micro-op-level workloads. Preliminary results demonstrate that the compiler generates competitive bit-serial code within $1.08\times$ and $1.54\times$ of hand-optimized digital and analog PIM baselines. Our code is publicly available at https://github.com/UVA-LavaLab/PIMsynth.