Yushen Zhang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Yushen Zhang has a total of 32 co-authors. Here are the top co-authors by number of shared publications:
- Tsun-Ming Tseng
Technical University of Munich, Munich, Bavaria, Germany
9 shared publications - Ulf Schlichtmann
Technical University of Munich, Munich, Bavaria, Germany
9 shared publications - Mengchu Li
Chair of Electronic Design Automation, Technical University of Munich, Munich, Germany
5 shared publications - Siyuan Liang
The Chinese University of Hong Kong, Shatin, Hong Kong
5 shared publications - Tsung-Yi Ho
The Chinese University of Hong Kong
4 shared publications - Ismail Emre Araci
Department of Bioengineering, Santa Clara University, Santa, USA
3 shared publications
Latest Publications
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-2
Late Breaking Results: "Describing" Your Way to a Functional Microfluidic Chip
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-2
Open AccessLate Breaking Results: "Describing" Your Way to a Functional Microfluidic Chip
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
LiPCon: A Physics-Aware Spatially Resolved Light Penetration Compensation Method for Low-Cost 3D-Printed Microfluidics
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccessLiPCon: A Physics-Aware Spatially Resolved Light Penetration Compensation Method for Low-Cost 3D-Printed Microfluidics
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/Ground Plane Synthesis
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccessBLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/Ground Plane Synthesis
- Open Access
- 20 January 2025
- Published by Association for Computing Machinery (ACM)
- p. 1357-1363
3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric Control
3D printing has revolutionized microfluidic device fabrication, enabling rapid prototyping and intricate geometries. However, designing lab-on-a-chip systems remains challenging. In microfluidic devices, precise control over fluid behavior is crucial, requiring careful attention to both timing and volume. Current state-of-the-art design automation tools for microfluidics have limitations, particularly in addressing the specific challenges of 3D-printed microfluidics and user-defined timing and volumetric constraints, and no design synthesis tool exists targeting these domains. We present 3M-DeSyn, a novel design synthesis method for 3D-printed microfluidics that incorporates timing and volumetric constraints and outputs print-ready 3D modeling files. It automates the design process, allowing users to specify schematics and desired flow control parameters. The underlying methodology is based on mathematical modeling of fluidic behavior and utilizes constraint optimization programming to find optimized solutions. Experimental results show significant improvements in design time while enabling rapid development of custom microfluidic systems.
- 20 January 2025
- Published by Association for Computing Machinery (ACM)
- p. 1357-1363
Open Access3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric Control
3D printing has revolutionized microfluidic device fabrication, enabling rapid prototyping and intricate geometries. However, designing lab-on-a-chip systems remains challenging. In microfluidic devices, precise control over fluid behavior is crucial, requiring careful attention to both timing and volume. Current state-of-the-art design automation tools for microfluidics have limitations, particularly in addressing the specific challenges of 3D-printed microfluidics and user-defined timing and volumetric constraints, and no design synthesis tool exists targeting these domains. We present 3M-DeSyn, a novel design synthesis method for 3D-printed microfluidics that incorporates timing and volumetric constraints and outputs print-ready 3D modeling files. It automates the design process, allowing users to specify schematics and desired flow control parameters. The underlying methodology is based on mathematical modeling of fluidic behavior and utilizes constraint optimization programming to find optimized solutions. Experimental results show significant improvements in design time while enabling rapid development of custom microfluidic systems.
- Open Access
- 5 August 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 44 (2) , 469-482
Manufacturing Cycle Time Optimization for Inkjet-Printed Electronics
Inkjet-printed electronics has attracted considerable attention for low-cost mass production. High-density inkjet-printed designs can benefit from printing and drying in batches to avoid defects due to undesired ink redistribution and ink merging. The state-of-the-art approach decomposes the design into small objects, assigns the objects to different layers to be printed in different iterations, and minimizes the number of layers to reduce the number of iterations. However, it overlooks the differences in the printing and drying time between different layers and thus cannot properly model the impact of different layer assignment solutions on the manufacturing cycle time. In this work, we propose a row-based printing model that simulates the inkjet-printing mechanism and an integral Gaussian drying model that evaluates the local evaporation rate to approximate the printing and drying process of inkjet-printed manufacturing. Based on these models, we propose a mixed-integer-linear programming (MILP) method called the manufacturing model to minimize the manufacturing cycle time and avoid defects by optimally assigning objects to different iterations to be printed and dried in batches. Experimental results confirm that, compared with the preliminary work, manufacturing using our optimized solutions required up to 42.7% less time.
- 5 August 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 44 (2) , 469-482
Open AccessManufacturing Cycle Time Optimization for Inkjet-Printed Electronics
Inkjet-printed electronics has attracted considerable attention for low-cost mass production. High-density inkjet-printed designs can benefit from printing and drying in batches to avoid defects due to undesired ink redistribution and ink merging. The state-of-the-art approach decomposes the design into small objects, assigns the objects to different layers to be printed in different iterations, and minimizes the number of layers to reduce the number of iterations. However, it overlooks the differences in the printing and drying time between different layers and thus cannot properly model the impact of different layer assignment solutions on the manufacturing cycle time. In this work, we propose a row-based printing model that simulates the inkjet-printing mechanism and an integral Gaussian drying model that evaluates the local evaporation rate to approximate the printing and drying process of inkjet-printed manufacturing. Based on these models, we propose a mixed-integer-linear programming (MILP) method called the manufacturing model to minimize the manufacturing cycle time and avoid defects by optimally assigning objects to different iterations to be printed and dried in batches. Experimental results confirm that, compared with the preliminary work, manufacturing using our optimized solutions required up to 42.7% less time.
- Open Access
- 23 June 2024
- Published by Association for Computing Machinery (ACM)
- p. 1-2
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Control channels on microfluidic large-scale integration (mLSI) chips are prone to blockage and leakage defects. In this work, we propose a built-in self-test (BIST) method that drastically improves the test efficiency. Given n to-be-tested control channels, we reduced the number of test patterns for blockage and leakage tests from [EQUATION] to 1, and from ⌈log2(n + 1)⌉ to ⌈log2(χ(G) + 1)⌉, respectively, where χ(G) denotes the vertex chromatic number of a graph G consisting of n vertices. We fabricated our design and demonstrated the feasibility and efficiency of our method.
- 23 June 2024
- Published by Association for Computing Machinery (ACM)
- p. 1-2
Open AccessLate Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Control channels on microfluidic large-scale integration (mLSI) chips are prone to blockage and leakage defects. In this work, we propose a built-in self-test (BIST) method that drastically improves the test efficiency. Given n to-be-tested control channels, we reduced the number of test patterns for blockage and leakage tests from [EQUATION] to 1, and from ⌈log2(n + 1)⌉ to ⌈log2(χ(G) + 1)⌉, respectively, where χ(G) denotes the vertex chromatic number of a graph G consisting of n vertices. We fabricated our design and demonstrated the feasibility and efficiency of our method.
- Open Access
- 23 June 2024
- Published by Association for Computing Machinery (ACM)
- p. 1-6
LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
After decades of development, flow-based microfluidic biochips have become an increasingly attractive platform for biochemical experiments. The fluid transportation and the on-chip device operation are controlled by microvalves, which are driven by external pneumatic controllers. To meet the increasingly complex experimental demands, the number of microvalves has significantly increased, making it necessary to adopt multiplexers (MUXes) for the actuation of microvalves. However, existing MUX designs have limited coding capacities, resulting in area overhead and excessive chip-to-world interface. This paper proposes a novel gate structure for modifying the current MUX architecture, along with a mixed coding strategy that achieves the maximum coding capacity within the modified MUX architecture. Additionally, an efficient synthesis tool for the mixed-coding-based MUXes (LaMUXes) is presented. Experimental results demonstrate that the LaMUX is exceptionally efficient, substantially reducing the usage of pneumatic controllers and microvalves compared to existing MUX designs.
- 23 June 2024
- Published by Association for Computing Machinery (ACM)
- p. 1-6
Open AccessLaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
After decades of development, flow-based microfluidic biochips have become an increasingly attractive platform for biochemical experiments. The fluid transportation and the on-chip device operation are controlled by microvalves, which are driven by external pneumatic controllers. To meet the increasingly complex experimental demands, the number of microvalves has significantly increased, making it necessary to adopt multiplexers (MUXes) for the actuation of microvalves. However, existing MUX designs have limited coding capacities, resulting in area overhead and excessive chip-to-world interface. This paper proposes a novel gate structure for modifying the current MUX architecture, along with a mixed coding strategy that achieves the maximum coding capacity within the modified MUX architecture. Additionally, an efficient synthesis tool for the mixed-coding-based MUXes (LaMUXes) is presented. Experimental results demonstrate that the LaMUX is exceptionally efficient, substantially reducing the usage of pneumatic controllers and microvalves compared to existing MUX designs.
- Open Access
- 18 May 2024
- Published by Springer Nature in Communications Engineering
- Vol. 3 (1) , 1-13
Open-source interactive design platform for 3D-printed microfluidic devices
Microfluidics and 3D printing offer exciting opportunities for the development of new technologies and applications in the fields of biology, chemistry, and medicine. However, the design of 3D-printed microfluidic devices remains a challenging and complex task, requiring specialized knowledge and expertise in fluid mechanics, 3D modeling, and 3D printing technology. Currently, there are very few tools helping engineers to do the labor-intensive process of designing microfluidic devices, let alone any tools that can help them design microfluidic devices for 3D printing. In this work, we introduce Flui3d, an interactive software platform for designing microfluidic devices for 3D printing. Flui3d offers a standard parameterized component library, support for multi-layer design, and the ability to design and configure microfluidic devices without the need for specialized knowledge. Flui3d incorporates a distinctive Design-for-Manufacturing (DFM) function, facilitating seamless fabrication of the designed microfluidic devices using commercial consumer-grade printers. We discuss the key features and benefits of Flui3d and demonstrate them by designing examples of microfluidic devices. We also discuss the design complexity and the potential applications of Flui3d.
- 18 May 2024
- Published by Springer Nature in Communications Engineering
- Vol. 3 (1) , 1-13
Open AccessOpen-source interactive design platform for 3D-printed microfluidic devices
Microfluidics and 3D printing offer exciting opportunities for the development of new technologies and applications in the fields of biology, chemistry, and medicine. However, the design of 3D-printed microfluidic devices remains a challenging and complex task, requiring specialized knowledge and expertise in fluid mechanics, 3D modeling, and 3D printing technology. Currently, there are very few tools helping engineers to do the labor-intensive process of designing microfluidic devices, let alone any tools that can help them design microfluidic devices for 3D printing. In this work, we introduce Flui3d, an interactive software platform for designing microfluidic devices for 3D printing. Flui3d offers a standard parameterized component library, support for multi-layer design, and the ability to design and configure microfluidic devices without the need for specialized knowledge. Flui3d incorporates a distinctive Design-for-Manufacturing (DFM) function, facilitating seamless fabrication of the designed microfluidic devices using commercial consumer-grade printers. We discuss the key features and benefits of Flui3d and demonstrate them by designing examples of microfluidic devices. We also discuss the design complexity and the potential applications of Flui3d.
- Open Access
- 26 March 2023
- Published by Association for Computing Machinery (ACM)
- p. 53-61
FXT-Route
In high-performance printed circuit boards (PCBs), adding serpentine delay lines is the most prevalent delay-matching technique to balance the delays of time-critical signals. Serpentine topology, however, can induce simultaneous accumulation of the crosstalk noise, resulting in erroneous logic gate triggering and speed-up effects. The state-of-the-art approach for crosstalk alleviation achieves waveform integrity by enlarging wire separation, resulting in an increased routing area. We introduce a method that adopts spiral delay lines for delay matching to mitigate the speed-up effect by spreading the crosstalk noise uniformly in time. Our method avoids possible routing congestion while achieving a high density of transmission lines. We implement our method by constructing a mixed-integer-linear programming (MILP) model for routing and a quadratic programming (QP) model for spiral synthesis. Experimental results demonstrate that our method requires, on average, 31% less routing area than the original design. In particular, compared to the state-of-the-art approach, our method can reduce the magnitude of the crosstalk noise by at least 69%.
- 26 March 2023
- Published by Association for Computing Machinery (ACM)
- p. 53-61
Open AccessFXT-Route
In high-performance printed circuit boards (PCBs), adding serpentine delay lines is the most prevalent delay-matching technique to balance the delays of time-critical signals. Serpentine topology, however, can induce simultaneous accumulation of the crosstalk noise, resulting in erroneous logic gate triggering and speed-up effects. The state-of-the-art approach for crosstalk alleviation achieves waveform integrity by enlarging wire separation, resulting in an increased routing area. We introduce a method that adopts spiral delay lines for delay matching to mitigate the speed-up effect by spreading the crosstalk noise uniformly in time. Our method avoids possible routing congestion while achieving a high density of transmission lines. We implement our method by constructing a mixed-integer-linear programming (MILP) model for routing and a quadratic programming (QP) model for spiral synthesis. Experimental results demonstrate that our method requires, on average, 31% less routing area than the original design. In particular, compared to the state-of-the-art approach, our method can reduce the magnitude of the crosstalk noise by at least 69%.
- 11 October 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 42 (6) , 1939-1950
Integrated Test Module Design for Microfluidic Large-Scale Integration
Microfluidic large-scale integration (mLSI) is a promising lab-on-a-chip platform for high-throughput bio-applications. Due to the high integration scale and the small feature size, control channels on mLSI chips are prone to blockage and leakage defects, which may lead to faulty behavior of valves and erroneous experimental results. Thus, mLSI chips need to be tested before usage. Current mLSI-tests are mostly performed in a straightforward way by testing each valve individually, which is very time-consuming and error-prone. As the integration scale of mLSI chips keeps increasing, there is a pressing demand for more efficient test approaches. This work proposes the first built-in-self-test (BIST) method for mLSI with an integrated test module design. Instead of testing individual valves, the proposed method directly tests the control channels and thus greatly improves the test efficiency. Only n2 and log2(n+1)test operations are required to test the blockage and leakage defects, respectively, of n control channels. The proposed test module consumes moderate area overhead and the test method is easy to operate. Neither specialized software nor external pressure sensors are required for carrying out the tests. Experiments show that our test approach is sensitive enough to detect defects that have a feature size as small as 10μm and that are several centimeters away from the test module.
- 11 October 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 42 (6) , 1939-1950
Integrated Test Module Design for Microfluidic Large-Scale Integration
Microfluidic large-scale integration (mLSI) is a promising lab-on-a-chip platform for high-throughput bio-applications. Due to the high integration scale and the small feature size, control channels on mLSI chips are prone to blockage and leakage defects, which may lead to faulty behavior of valves and erroneous experimental results. Thus, mLSI chips need to be tested before usage. Current mLSI-tests are mostly performed in a straightforward way by testing each valve individually, which is very time-consuming and error-prone. As the integration scale of mLSI chips keeps increasing, there is a pressing demand for more efficient test approaches. This work proposes the first built-in-self-test (BIST) method for mLSI with an integrated test module design. Instead of testing individual valves, the proposed method directly tests the control channels and thus greatly improves the test efficiency. Only n2 and log2(n+1)test operations are required to test the blockage and leakage defects, respectively, of n control channels. The proposed test module consumes moderate area overhead and the test method is easy to operate. Neither specialized software nor external pressure sensors are required for carrying out the tests. Experiments show that our test approach is sensitive enough to detect defects that have a feature size as small as 10μm and that are several centimeters away from the test module.