Hossein Rezaei

The rapid growth of multimedia content in consumer electronics devices in edge scenarios, such as smart camera sensors, autonomous navigation, and wireless security systems, necessitates more efficient communication systems. Semantic communication (SemCom) systems enhance transmission efficiency by focusing on semantic content. However, design challenges persist, including limitations in generalizing semantic source coding, maintaining channel-agnostic performance, and ensuring robustness against channel noise. We propose a novel SemCom architecture leveraging vector quantization(VQ) and edge inference to enhance semantic content representation. This architecture models the underlying data distribution, enabling efficient and accurate predictions of unseen data. By transmitting only the indices of relevant codebook vectors extracted at the edge device, our SemCom architecture minimizes communication overhead while maintaining robust semantic content representation. The system focuses on two receiver tasks, reconstruction and classification. Evaluations demonstrate the system’s superior performance over better portable graphics (BPG) and joint source-channel coding (JSCC) in terms of perceptual quality, with low-density parity-check (LDPC) coding across both additive white Gaussian noise (AWGN) and Rayleigh flat fading channels, as well as classification accuracy with polar coding over the AWGN channel. Experimental results reveal a 25% reduction in transmission overhead compared to JSCC with LDPC coding with a code rate of 0.5 for varying signal-to-noise ratio (SNR)s, while maintaining lower overall computational complexity. Additionally, the model is validated using out-of-distribution and high-resolution datasets, validating its adaptability and scalability to diverse consumer electronics scenarios. The classification model achieved 85.52% training accuracy, with 72.25% and 50.88% accuracy at high and low SNR levels, respectively.

Over the past decade, polar codes have received significant attraction and have been selected as the coding method for the control channel in fifth-generation (5G) wireless communication systems. However, conventional polar codes are reliant solely on binary ( $2 \times 2$ ) kernels, which restricts their block length to being only powers of 2. In response, multi-kernel (MK) polar codes have been proposed as a viable solution to achieve increased flexibility in code length. This article proposes unrolled and pipelined architectures for encoding both systematic and nonsystematic MK polar codes, capable of high-throughput encoding of codes constructed with binary, ternary ( $3 \times 3$ ), or binary-ternary mixed kernels. Furthermore, two novel nonsystematic stage-folded encoders, designed to minimize resource usage, have been introduced for the encoding of pure-ternary and MK codes. The proposed MK encoders additionally provide the functionality of dynamic kernel assignment. The proposed architectures exhibit an unprecedented level of flexibility by supporting 83 different codes and offering various architectures that provide tradeoffs between throughput and resource consumption. The FPGA implementation results demonstrate that a partially pipelined polar encoder of size $N=4096$ operating at a frequency of 270 MHz gives a throughput of 1080 Gb/s. In addition, a new compiler scripted in Python is introduced to automatically generate HDL modules for the desired encoders. By inserting the desired parameters, a designer can simply obtain all the necessary VHDL files for FPGA implementation.

Polar codes have received growing attention in the past decade and have been selected as the coding scheme for the control channel in the fifth generation (5G) wireless communication systems. However, the conventional polar codes have only been constructed by binary ( $2\times 2$ ) kernel, which poses block length limitation to powers of 2. To attain more flexible block lengths, multi-kernel polar codes are proposed. In this paper, a combinational architecture for multi-kernel polar codes with high throughput is proposed based on successive cancellation decoding algorithm. The proposed scheme can decode pure-binary, pure-ternary ( $3\times 3$ ), and binary-ternary mixed polar codes. The decoder’s architecture is rate-flexible, meaning that a new code rate can be assigned to the decoder at every clock cycle. The proposed architecture is validated by FPGA implementation, and the results reveal that a code of size $N=81$ achieves the coded throughput of 1664.5 Mbps. A Python-based polar compiler is also proposed to automatically generate the HDL modules for target decoders. A designer can input the target block length and kernel ordering of a polar code and get the required VHDL files automatically.

Semantic communication represents a promising roadmap toward achieving end-to-end communication with reduced communication overhead and an enhanced user experience. The integration of semantic concepts with wireless communications presents novel challenges. This paper proposes a flexible simulation software that automatically transmits semantic segmentation map images over a communication channel. An additive white Gaussian noise (AWGN) channel using binary phase-shift keying (BPSK) modulation is considered as the channel setup. The well-known polar codes are chosen as the channel coding scheme. The popular COCO-Stuff dataset is used as an example to generate semantic map images corresponding to different signal-to-noise ratios (SNRs). To evaluate the proposed software, we have generated four small datasets, each containing a thousand semantic map samples, accompanied by comprehensive information corresponding to each image, including the polar code specifications, detailed image attributes, bit error rate (BER), and frame error rate (FER). The capacity to generate an unlimited number of semantic maps utilizing desired channel coding parameters and preferred SNR, in conjunction with the flexibility of using alternative datasets, renders our simulation software highly adaptable and transferable to a broad range of use cases.

Polar codes have been selected as the channel coding scheme for control channel in the fifth generation (5G) communication system thanks to their capacity achieving characteristics. However, the traditional polar codes support only codes constructed by binary (2x2) kernel which limits the code lengths to powers of 2. Multi-kernel polar codes are proposed to achieve flexible block length. In this paper, the first combinational decoder for multi-kernel polar codes based on successive cancellation algorithm is proposed. The proposed decoder can decode pure-binary and binary-ternary (3x3) mixed polar codes. The architecture is rate-flexible with the capability of online rate assignment and supports any kernel sequences. The FPGA implementation results reveal that for a code of length N = 48, the coded throughput of 812.1 Mbps can be achieved.

Over the past decade, polar codes have received significant traction and have been selected as the coding method for the control channel in fifth-generation (5G) wireless communication systems. However, conventional polar codes are reliant solely on binary (2x2) kernels, which restricts their block length to being only powers of 2. In response, multi-kernel (MK) polar codes have been proposed as a viable solution to attain greater code length flexibility. This paper proposes an unrolled architecture for encoding both systematic and non-systematic MK polar codes, capable of high-throughput encoding of codes constructed with binary, ternary (3x3), or binary-ternary mixed kernels. The proposed scheme exhibits an unprecedented level of flexibility by supporting 83 different codes and offering various architectures that provide trade-offs between throughput and resource consumption. The FPGA implementation results demonstrate that a partially-pipelined polar encoder of size N=4096 operating at a frequency of 270 MHz gives a throughput of 1080 Gbps. Additionally, a new compiler implemented in Python is given to automatically generate HDL modules for the desired encoders. By inserting the desired parameters, a designer can simply obtain all the necessary VHDL files for FPGA implementation.

Semantic communication is considered the future of mobile communication, which aims to transmit data beyond Shannon’s theorem of communications by transmitting the semantic meaning of the data rather than the bit-by-bit reconstruction of the data at the receiver’s end. The semantic communication paradigm aims to bridge the gap of limited bandwidth problems in modern high-volume multimedia application content transmission. Integrating AI technologies with the 6G communications networks paved the way to develop semantic communication-based end-to-end communication systems. In this study, we have implemented a semantic communication-based end-to-end image transmission system, and we discuss potential design considerations in developing semantic communication systems in conjunction with physical channel characteristics. A Pre-trained GAN network is used at the receiver as the transmission task to reconstruct the realistic image based on the Semantic segmented image at the receiver input. The semantic segmentation task at the transmitter (encoder) and the GAN network at the receiver (decoder) is trained on a common knowledge base, the COCO-Stuff dataset. The research shows that the resource gain in the form of bandwidth saving is immense when transmitting the semantic segmentation map through the physical channel instead of the ground truth image in contrast to conventional communication systems. Furthermore, the research studies the effect of physical channel distortions and quantization noise on semantic communication-based multimedia content transmission.

Polar codes have been receiving increased attention for application in beyond 5G networks. They offer low-complexity decoding algorithm and can achieve symmetric channel capacity. However, the majority of research works have focused on the codes constructed by the binary kernel (2 × 2 polarization matrix) which bounds the code length to an integer power of 2. Multi-kernel polar codes have been proposed as a method that allows the construction of polar codes with sizes different from powers of 2 by mixing multiple kernels of different dimensions. A hardware implementation based on the successive cancellation (SC) algorithm found in the literature shows that it suffers from a long decoding latency. In this paper, we design and implement a multi-kernel decoder based on the fast-simplified SC (fast-SSC) algorithm to decrease the decoding latency. It can decode any code constructed by binary and ternary (3 × 3) kernels featuring flexible code length, code rate, and kernel sequence. FPGA implementation results reveal that a polar code of length N = 1536, rate R = 1/2 with Processing Element ( P_e ) value of P_e = 240, gains 84.6% lower latency compared to the original algorithm. Also, the architecture supports polar codes constructed by purely-binary and purely-ternary kernels. A polar code of length N = 1024, rate R = 1/2, and P_e = 120 achieves an information throughput of 432 Mbps.