Yong-Sang Kim

The bias stress reliability of double-gate (DG) amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) is systematically investigated with an emphasis on the asymmetric behavior between the bottom-gate (BG) and top-gate (TG) interfaces. Under positive bias stress (PBS), a significant positive threshold voltage ( V _TH ) shift is observed only when stress is applied to BG, whereas negligible variation is detected under TG stress. To clarify the origin of this asymmetry, BG a-IGZO TFTs are fabricated under varying radio-frequency (RF) sputtering power. Electrical analysis shows that the interface trap state density decreases at moderate RF power and increases at higher power, indicating a trade-off between improved surface migration and defect generation caused by ion bombardment. XPS and AFM confirm that the chemical composition and surface morphology of the a-IGZO films remain nearly unchanged with RF power, suggesting that the instability is not governed by bulk properties. Instead, the V _TH shift is dominated by defect states at the bottom interface. The asymmetric behavior in DG a-IGZO TFTs is therefore attributed to differences in interface quality arising from deposition sequence and plasma-induced damage. These findings provide insight into the mechanism of bias stress instability and highlight the importance of interface engineering for improving the reliability of oxide TFTs.

This study investigates the direct effects of the cross-linker 1,6-bis(trichlorosilyl)hexane (BTCSH) with the surface of amorphous indium–gallium–zinc oxide (IGZO) and its consequences for thin-film transistor operation. To elucidate the impact of BTCSH, a pristine device and a BTCSH-treated device were examined, the latter being fabricated by spin-coating a BTCSH-containing solution onto the pristine device and subsequently annealing at 200 °C to remove the solvent and retain only BTCSH. As a result, BTCSH-treated devices exhibited a lower threshold voltage (VTH) of −0.95 V, higher field-effect mobility (μFE) of 8.13 cm2/V s, and lower subthreshold swing of 0.24 V/dec compared to those of pristine devices. Under positive gate bias stress, the VTH shift decreased from 5.5 V in the pristine device to 4.0 V after BTCSH treatment. These improved performances and reliability are attributed to the reduction of weakly bonded oxygen and the formation of oxygen vacancies (VO) at the back-channel surface. Consequently, the reaction mechanism of the BTCSH cross-linker on the IGZO surface should be considered during process design, as it affects both defect states and device reliability.

This work proposes an organic-inorganic bilayer passivation composed of spin-coated PMMA and sol-gel-derived HfO₂ to improve the stability and suppress electrical degradation of solution-processed a-IGZO TFTs. The influence of the passivation layer stacking sequence on device properties was investigated through absorbance spectroscopy and electrical measurements.Results showed that depositing HfO₂ directly onto a-IGZO causes severe interfacial degradation, whereas placing the PMMA buffer layer beneath HfO₂ effectively preserves the active channel. XPS depth profiling and chemical analysis revealed that placing the PMMA buffer layer beneath the HfO₂ film effectively prevents excessive Hf diffusion, thereby reducing oxygen vacancy-related defects at the back channel from 42.3% to 33.3%. Consequently, the optimised bilayer structure significantly decreases threshold voltage shift under positive bias stress and minimizes the hysteresis window to 0.15 V. Furthermore, waterproof tests confirmed that the PMMA/HfO₂ bilayer provides better moisture barrier performance, effectively suppressing water-induced electrical degradation. This study demonstrates that the organic-inorganic bilayer passivation effectively enhances the environmental stability and electrical reliability of solution-processed a-IGZO TFTs.

This article presents novel scan driver circuits for active-matrix display panels based on CMOS logic gates and hybrid thin-film transistor (TFT) technology. In the proposed design, the logic and output parts are separated and implemented using distinct methods to address the limitations of amorphous indium gallium zinc oxide (a-IGZO) TFTs and single-channel-type circuits. Two types of scan driver circuits were designed and simulated to meet a refresh rate of 120 Hz and a resolution of $1440\times 2560$ . The fabricated circuits were evaluated by measuring the output voltage waveforms across ten stages under the same simulation conditions, confirming their operational feasibility. The proposed method enhances the flexibility of circuit design for hybrid TFT-based high-resolution display panels.

We propose a scan driver circuit based on p-type low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) capable of positive and negative dual output (PNDO) signals, enabling to activate n-type and p-type TFTs in LTPS and oxide TFT-based pixel circuits. The proposed circuit outputs PNDOs with improved falling characteristics by controlling the output timing and using a bootstrapping method. Power consumption and the circuit area are reduced by generating PNDO signals using a single control part. In addition, the fabricated circuit successfully generated PNDO signals.