Xing Zhao

True random number generator (TRNG) is an essential part of cryptographic systems. In this paper, a high bit rate and self-stable probability TRNG based on spin-orbit torque magnetic tunnel junction (SOT-MTJ) is proposed. The TRNG reaches 16.7 Mb/s bit rate and 93.62 pJ/bit energy consumption for a single cell. In addition, the TRNG achieves a stable probability of random numbers regardless of the voltage and device to device variation. The random bits have passed the National Institute of Standards and Technology statistical test suite. Our results provide a candidate of high bit rate TRNG for IoT security applications.

Organic field-effect transistors (OFETs) based on n-type donor-acceptor (D-A) conjugated copolymer are at the forefront of research in organic electronics. Yet, an understanding of the fundamental aspects of their charge transport, in particular the relevant traps, remains limited. In this study, we show that the low-frequency noise (LFN) of n-type OFETs based on N2200 exhibits 1/f behavior. The normalized power spectrum density of the drain current (I_D), namely (S_Id/I_D²), varies similarly as (g_m/I_D)² with gm being the transconductance, indicating the carrier number fluctuations. Examination on the annealing temperature and air stability of the devices with different contacts using LFN reveal sizably varied trap density, conforming the correlation between performance degradation and defect states. Thus, LFN provides quantitative insight into the charge transport behind.

The core–shell junctionless MOSFET (CS-JL FET) meets the process requirements of FD-SOI technology. The transistor body comprises a heavily doped ultrathin layer (core linking the source and the drain), located underneath an undoped layer (shell). Drain current, transconductance, and capacitance characteristics demonstrate striking performance improvement compared with conventional junctionless MOSFETs. The addition of the shell results in one order of magnitude higher mobility (peak value), transconductance, and drive current. The doping and thickness of the core can be engineered to achieve a positive threshold voltage for normally-off operation. The CS-JL FET is compatible with back-biasing and downscaling schemes. The physical mechanisms are revealed by emphasizing the roles of the main device parameters.

In this work, we demonstrate an STT-MRAM device with double reference layer that shows extremely low critical switching current density. A synthetic antiferromagnetic (SAF) layer [Co/Pt]n/Ru/[Co/Pt]m is used as the upper reference layer in the STT-MTJ device with perpendicular magnetic anisotropy (PMA) which can apply extra spin transfer torque to the free layer in the process of data writing. The ac R-I experimental results show that when the magnetization directions of upper and nether reference layer are antiparallel state, the JC is only 1.230 MA/cm2 for AP2P and 1.867 MA/cm2 for P2AP, when the pulse width is 10ns, which is more than $5\times $ lower than the classical single reference layer STT-MTJ device with the close thermal stability. Our work provides a new way to achieve the ultra-low power STT-MRAM for IoT application.

Organic–inorganic hybrid perovskites are widely used in photodetection owing to their high optical absorption coefficients. A variety of research has been conducted on perovskite phototransistors and their optoelectronic properties, but the exploration of the influence of contact resistance remains limited. In this work, we employed the transmission-line method to separate the contact resistance Rc × W (ranging from 4.81 × 104 to 4.77 × 103 Ω cm) and the channel resistance Rch × W (ranging from 1.93 × 104 to 1.16 × 104 Ω cm) of (PEA)2SnI4 perovskite phototransistors at different light intensities (520 nm, ranging from 0 to 2550 μW/cm2). Further analysis reveals that illumination-induced accumulation of charge carriers at the metal/semiconductor interface reduces the Schottky barrier. Approximately 90% of the observed increase in photocurrent can be attributed to the reduction in the contact resistance. Our finding underscores the crucial role of charge injection in influencing perovskite-based phototransistors.

Organic electrochemical transistors (OECTs) are now widely investigated for their potential use in brain-inspired neuromorphic computation. In this paper, chitosan-gated OECTs are proposed as the neuromorphic devices. The proton conductive chitosan employed as the dielectric can provide low-voltage operation and synapse-like functions for such device via its electric-double-layer (EDL) capacitive effect. Two wiring schemes are utilized for such devices to emulate two different types of short-term synaptic plasticity: potentiation (STP) and depression (STD). These schemes are further integrated into a novel neuromorphic circuit to implement direction selectivity. The achieved direction selectivity is subsequently employed as a temporal-coding method for the recognition of dynamic handwriting. This study demonstrates the tremendous potential of chitosan-gated OECT in neuromorphic application, and it is expected to accelerate the development of next-generation artificial intelligence systems.

Organic field-effect transistors (OFETs) have been widely studied, but there are still challenges to achieving large-scale integration in organic complementary metal–oxide–semiconductor (CMOS) circuits. In this article, we discuss the issues on organic CMOS circuits from a device perspective. Our discussion begins with a systematic analysis of the principal parameters of the building block, a CMOS inverter, including gain, noise margin, and power dissipation, as well as the relevant challenges and the potential solutions. We then review state-of-the-art organic CMOS inverters and their fabrications. Finally, we focus on the approaches to optimize organic CMOS circuits from a specific point of view of the contact engineering, particularly for N-type OFETs.

Prediction of electrostatic discharge (ESD) protection performance is critical for estimating reliability in the IC design. However, due to the large injection and deep hysteresis encountered in the snapback of ESD devices, the failure current of ESD devices is hard to be predicted by simulation. In this article, a TCAD simulation method using the shot noise model to predict the failure current of ESD devices is proposed for the first time. The transmission line pulse (TLP) test results show the same trend as the simulation results, indicating that this method is convenient and effective to predict the ESD failure current. It is promising applications for the design of ESD devices and full-chip network protection.

N-type organic field-effect transistors have suffered from poor environmental instability. Here, we report that, by using nickel (Ni) instead of the commonly used gold (Au) as contact electrodes, n-type polymer transistors showed much improved stability upon annealing in nitrogen and exposure to air. In particular, Au-contacted devices exhibited pronounced ambipolar conduction whereas Ni-contacted devices retained fairly good unipolar properties. The results are important to build stable n-type polymer transistors at low cost.