Chen Pan

Quantum geometry, describing the inherent geometric structure of electron wavefunctions in momentum space, transcends the traditional charge degree of freedom and provides a novel physical basis for information encoding and processing. The key to such new computing paradigms is the nonvolatile electrical programming of quantum geometric states at room temperature, which, however, has not been established. Here, we demonstrate ferroelectrically switchable quantum geometry in few-layer WTe₂, which uniquely enables complementary convolutional processing. By employing the intrinsic coupling between ferroelectric polarization and quantum geometry in few-layer WTe₂, we show that the second- and third-order nonlinear anomalous Hall effects (NLAHE) can be deterministically and electrically switched in a nonvolatile and correlated manner. The switching is robust at room temperature for ~10⁴ cycles and retention of ~10⁵s. Furthermore, leveraging the opposite switching behaviors of second- and third-order NLAHE at room temperature, we demonstrate complementary in-memory computing and implement a hardware-level complementary convolution kernel. This kernel overcomes the inherent directional specificity of conventional convolutional networks and achieves a texture recognition accuracy of 98%, thereby illustrating a viable pathway towards physics-native computing through exploiting exotic physics in quantum materials.

Reconfigurable field-effect transistors (RFETs) based on ambipolar two-dimensional (2D) semiconductors provide a versatile platform for multifunctional logic and neuromorphic computing. Traditional RFET architectures typically rely on horizontally arranged multi-gate structures to create tunable homojunctions, a design that imposes significant constraints on lateral scaling due to the required physical gaps between adjacent gates. In this work, we report a reconfigurable WSe2 transistor that achieves polarity control through a complementary electrostatic shielding mechanism. By employing an asymmetric contact configuration consisting of a top-contacted source and a bottom-contacted drain, we demonstrate that these electrodes can selectively shield the top-gate and back-gate fields, respectively. This architecture ensures that the back gate independently modulates carrier injection at the source junction while the top gate governs injection at the drain junction. Such a vertically decoupled dual-gating scheme enables a single device to exhibit robust reconfigurable n- and p-type characteristics with a scaled lateral channel length of ∼500 nm, which is a notable improvement over conventional split-gate RFETs based on 2D materials (∼2 μm). Furthermore, we demonstrate a complementary logic inverter based on this device that achieves a static power consumption below 10 pW. This study introduces a novel physical principle for RFET operation and offers a promising pathway for the continuous scaling of reconfigurable 2D electronics.

Real-time perception of dynamic visual scenes requires efficient extraction of spatiotemporal features. However, conventional image sensors fail to capture inter-pixel correlations, leading to redundant data transfer, high power consumption and latency. Here, we present a non-pixelated in-materia retinomorphic sensor (IMRS) that exploits the intrinsic spatiotemporal dynamics and correlated distributions of photocarriers for visual information processing. Built on a large-area graphene/silicon heterostructure, the IMRS integrates circumferentially arranged sampling electrodes that harness the lateral photovoltaic effect to convert incident optical patterns into spatial carrier distributions, which are further encoded as object-shape-dependent photovoltages. Mimicking the lateral inhibition of biological retinas, this sensor enables in-sensor spatiotemporal perception without image reconstruction. We demonstrate human motion recognition with over 98% accuracy while compressing raw visual data from 10,000 to 48 bytes, reducing postprocessing networks parameters by two orders of magnitude. These results establish spatiotemporal photocarrier dynamics in low-dimensional heterostructures as a computational primitive for energy-efficient, ultralow-latency processing of high-dimensional spatiotemporal information.

Mechanical computing represents a highly promising paradigm for environment-adaptive information processing. However, existing implementations are generally constrained by limited architectural scalability, and their modes of application in practical scenarios remain insufficiently defined. Here, we develop a light-programmable mechanical computing system that not only performs scalable logic operations but also enables environment-adaptive optical camouflage. The system is based on a polyaniline composite film (PCF) that integrates light-responsive expansion–contraction elements with a flexible conductive layer. Light illumination dynamically modulates the conductive pathways, giving rise to optically controlled single-pole single-throw (SPST) and single-pole double-throw (SPDT) relays that reconfigure signal transmission routes. Interconnecting these relays enables the construction of basic logic gates and 2-bit full-adder circuits, establishing a scalable paradigm for light-programmable mechanical computation. Moreover, we implement an adaptive camouflage function that senses environmental textures and generates matching optical patterns, demonstrating potential for intelligent skin applications capable of environmental interaction. This work establishes a light-programmable, pathway-reconfigurable mechanical computing framework, expanding possibilities for autonomous and adaptive intelligent systems.

The relentless downscaling of integrated circuit systems imposes critical demands on spintronic technologies, particularly requiring superior storage density and efficient tunability beyond conventional magnetic-field approaches. A notable challenge persists in realizing multistate spintronic devices with electrical control at nanoscale. Here, we propose a breakthrough strategy for achieving bias-controlled giant tunneling magnetoresistance (TMR) for multistate memory applications. Our design uses two-dimensional (2D) half-metals hosting strongly localized spin states (LSSs) at the Fermi level as two ferromagnet layers in magnetic tunnel junctions (MTJs). Multiple memory states emerge from bias-driven alignment/misalignment of LSSs on two sides, generating sudden tunneling pathway changes and distinguishable TMR. First-principles quantum transport simulations on MTJs based on 2D VCl ₃ and FeCl ₂ reveal unprecedented bias-controlled and widely modulable TMR ratios spanning −194 to 2677% and −130 to 37,424%, respectively, accompanied by rare polarity switch capabilities. Our work opens a promising route for realizing electrical control of multistate spintronics.

Analog computing has gained increasing attention for its potential in artificial intelligence hardware. The computation in traditional analog systems relies on use of intrinsic physical quantities (e.g., resistance), which are prone to fluctuations due to environmental changes or repeated programming, leading to compromised precision. Here, we shift the reliance on intrinsic physical quantity of memory devices to geometric ratio of transistors, enabling ultrahigh-precision analog computation. We demonstrate an analog in-memory computing chip based on a standard complementary metal-oxide semiconductor process, achieving the highest precision reported to date. Enhanced by the proposed weight remapping technique, the chip realizes ultrahigh computing accuracy with a root mean square error of only 0.101% across multiple parallel vector-by-matrix multiplication operations. Moreover, our analog in-memory computing chip maintains high precision, with an error of 0.155 and 0.130% under environmental temperatures of −78.5° and 180°C, respectively. This work pushes the boundaries of analog computing precision by leveraging stable geometry feature of devices.

In-memory computing hardware based on memristors has emerged as a promising option for scientific computing due to its large-scale parallel data processing capability. However, the nonuniformity issue of the memristors renders the practical deployment of in-memory computing hardware complex, requiring peripheral circuits to ensure the accuracy of scientific computing, thereby resulting in increased power consumption. Here, we present a mortise-tenon–shaped (MTS) memristor with ultrahigh uniformity by introducing a mortise-shaped h-BN flake on the HfO ₂ switching layer. The MTS memristor exhibits ultrasmall cycle-to-cycle (~2.5%) and device-to-device (~6.9%) variations compared to the HfO ₂ memristor without the MTS structure. Furthermore, we use the MTS memristors to build a partial differential equation solver and demonstrate a convergence speed of solving the Poisson equation five times faster than the solver based on the traditional HfO ₂ memristors. This work provides a promising approach for notably reducing the hardware resources required for fast and high-accuracy scientific computing.