Sung-Mo Kang

This work presents a CMOS-compatible, energy-efficient, and trainable neuromorphic architecture employing LIF neurons, validated through mathematical analysis of the membrane potential dynamics. It is implemented in a modular $64\times 36$ crossbar array for temporal sequential detection of 36 alphanumeric patterns, each represented by an $8\times 8$ pixel input. A novel spike mismatch detection cell, implemented in UMC 65-nm CMOS technology, enables pixel-wise comparison using two mutually inhibiting LIF neurons and an output neuron that spikes only on mismatches. Column-wise mismatch spikes encode similarity, while a simplified analog winner-take-all (WTA) logic identifies the best-matching pattern and is capable of identifying both positional and density variations. Each modular cell occupies an area of approximately $608~\mu \text {m}^{2}$ , with an average power of $25.82~\mu $ W per column and energy of 64.55 pJ per inference (0– $2.5~\mu $ s), and Monte Carlo simulations showed process/temperature robustness. An accuracy of >95% was achieved under 2–3 pixel perturbations. Real-time validation with fixed alphanumeric inputs confirmed reliable operation at up to 1 MHz with $0.25~\mu $ s setup time. A hardware prototype for the proposed block using discrete ICs (SN7404, CD4007) further demonstrated precise spike generation and effective inhibition.

This article proposes a novel memristor emulator design capable of operating in the ultra-high-frequency range. The proposed memristor emulator, implemented using two nMOS transistors and a grounded MOS-capacitor, is designed and simulated in the Analog Design Environment of Cadence Virtuoso using a 90nm CMOS technology. It achieves a maximum operating frequency of 3 GHz, with a power consumption of 13.52 μW. The robustness of the proposed memristor emulator is validated through extensive simulations, including temperature variations, process corners, capacitance variations, and different combinations. Additionally, short-term non-volatility analysis has been conducted to evaluate its memory characteristics. The layout of the proposed memristor emulator is presented, along with pre-layout and post-layout simulations. Furthermore, hardware validation has been performed using commercial ICs (IRF840). Applications such as an 8:3 encoder, an adaptive neural network, and a ring oscillator circuit using the proposed memristor emulator are also reported in this article. The simulation results confirm that the memristive encoder functions correctly at 2 GHz and the ring oscillator generates an oscillation frequency greater than 2 GHz, demonstrating the emulator’s suitability for ultra-high-frequency applications.

Electronic neurons, such as integrate-and-fire models and memristor synapses, are key components of energy-efficient spiking neural network (SNN) systems. Current silicon-based models face challenges due to high transistor counts, large footprints, and excessive energy consumption. This brief presents a low-transistor count, energy-efficient neuron design. Our spiking signal-generating circuit consumes approximately 1.2 pJ per spike and uses a single capacitor as its only passive element, while occupying a layout area of 66.93 μm x 36.12 μm and operating on a 1 V power supply. We also highlight the driving capability and pattern recognition application of our proposed neuron model.

On 17 February 2025, the IEEE Board of Directors designated the BELLMAC-32 development as a historic milestone. Commemorative plaques will be placed on the walls of Nokia Bell Labs, Murray Hill, NJ, and the Computer History Museum in Mountain View, CA. The Bell Labs Murray Hill research center was where most of the BELLMAC-32 R&D work was performed, and a group in Holmdel, NJ (a location no longer part of Bell Labs) along with a group in Naperville, IL was involved as well. When the BELLMAC-32 technology was created, this was the key research center for AT&T Bell Laboratories. Today, Murray Hill is the US location for Nokia Bell Labs. The plaque citation summarizing the achievement and its significance reads: “Developed between 1976 and 1982, the Bell Laboratories BELLMAC-32 microprocessor series introduced many seminal design concepts, including 32-bit wide internal and external transfers, high-speed domino circuits to reduce complex logic gate delay times, a twin-tub CMOS process for improved power efficiency and performance, interconnect-centric logic design for signal delay reduction, gate-matrix layout which increased density, and instructions which implemented certain UNIX operating system and C programming language operations.”

Object detection and recognition are crucial for autonomous vehicles, surveillance systems, and human-computer interaction. We present a new fully complementary metal-oxide semiconductor (CMOS) circuit-based system for object detection and recognition using a Spiking Neural Network (SNN). Our holistic CMOS circuit integrates neuromorphic elements, including a leaky integrate-and-fire (LIF) neuron model, spike time-dependent plasticity (STDP) memristor synapse, and basic analog and digital building blocks. The learning mechanism is manifested by a completely different approach based on an array of XOR gates to recognize six different objects with 256 × 6 size crossbar arrays. This is the first-ever recognition mechanism of its kind. We also perform handwritten digit recognition using a 64 × 4 size array using grayscale conversion. The proposed system’s robustness is validated through process corner simulations, noise analysis, and temperature analysis. We also show the accuracy of our design for the digit recognition task using a confusion matrix plot, and the accuracy turns out to be 82.5 %. Our pioneering approach using a CMOS memristor-emulator STDP crosspoint array-based architecture achieves minimal energy consumption per neuron block, which amounts to ≈ 2.59 pJ per neuron block and an overall energy budget of 663.66 pJ for the entire system considering the object recognition task.

The IEEE Circuits and Systems Society (CASS) celebrated its 75th anniversary at the IEEE International Symposium on Circuits and Systems (ISCAS). A significant event was the “Past President Sharing Panel,” featuring insights from IEEE CASS Past Presidents Sung-Mo (Steve) Kang, Ljiljana Trajkovic, Maciej Ogorzalek, Franco Maloberti, and Amara Amara. Their presentations and panel discussions provided a comprehensive overview of the Society’s history and future direction, emphasizing diversity, innovation, and global collaboration to shape the future of circuits and systems.

This article is based on my presentation in the past-presidents panel at the IEEE International Symposium on Circuits and Systems (ISCAS2024) in Singapore on May 21, 2024. In this panel, a group of past presidents reflected on the past accomplishments of the CAS Society. My presentation was on how I have benefitted from experiences with and inspirations from eminent CAS Society (CASS) members. Due to limited time, it was not possible to prepare for many other deserving members, but only for a group of members whom I have had firsthand interactions with. This article begins with a brief review on the birth of the IEEE CAS Society from the Circuit Theory Group of IRE, followed by mentioning the founders of electrical science. Then, short highlights of distinguished CAS members, in particular, influential educators, creative researchers, impactful industry pioneers, professional leaders, and more recent leaders in WIE/WiCAS are provided. A one-pager list of active past and present CAS members is also provided, followed by a personal wish list for future success of CASS.

In the sound localization of species, short-term depression (STD) plays an important role in maintaining interaural timing difference (ITD) sensitivity. In this paper, a biomimetic spiking neural network (SNN) utilizing 2D synaptic devices for mimicking biological sound localization is presented. A two-terminal monolayer device is used as the artificial synapse, whose temporal conductance change mimics the STD of a synapse. Alpha synaptic current and leaky integrate-and-fire (LIF) neuron models are used for realistic cortical operation. Lateral inhibition and superior olivary nucleus (SON) are adopted to increase the acuteness, to compensate for the interaural level difference (ILD)-induced disturbance, and to enlarge the sound intensity range. By combining solid-state STD synapses and bio-plausible cortical models with an ITD-based coincidence detection mechanism to mimic the auditory brainstem processing, our SNN achieved sound localization with a human-level resolution of one degree.

A compact MOSFET-C floating/grounded meminductor emulator (MIE) model is presented for high operating frequency and low power operation. The proposed MIE uses only 22 MOSFETs and two capacitors. Its performance is theoretically analyzed and rigorously verified using the Cadence Virtuoso software and hardware prototypes. The proposed MIE operates appropriately for a wide range of frequencies up to 5 MHz with $590 \mu \text{W}$ power consumption at a 180nm CMOS technology node and manifests important signature properties. The MIE layout area in 180 nm CMOS technology is $13107.5 \mu \text{m}^{2}$ . To analyze the effects of statistical variations in MIE elements, extensive Monte Carlo simulations have been performed to demonstrate the robustness of the proposed MIE. For experimental validation, hardware prototypes have been developed and tested successfully. An MIE-based adaptive learning neuromorphic circuit is presented to show that it can mimic the behavioral responses of amoeba under varying environments such as temperature.

Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed and verified by simulation. Next, logic circuits such as ternary encoders, decoders and multiplexers are designed using these three basic gates. For further validation, a ternary 3-1 encoder was hardware-implemented successfully using in-house fabricated memristors and MOS transistors. Two different design approaches, namely the decoder-based method and the multiplexer-based method are introduced and applied to realize combinational logic circuits such as balanced ternary half-adder, multiplier, and numerical comparator. We simulate the circuits using 50nm CMOS technology parameters and BSIM models and present comparisons and analyses of the two design methods in view of the power consumption and component device counts, which can guide subsequent research and development of integrated multi-valued logic circuits. The decoder-based method has advantages both in terms of component numbers and power consumption, but the multiplexer-based method has the advantages of being based on a simple operating principle and ease of implementation.