Xiaowu Cai

A snapback-free MOS-triggered thyristor with modulated thyristor ratio (SFMR-MCT) has been developed for high-current pulsed power applications. The proposed device integrates a large-area N⁺ emitter and a compact P⁺ turn-off region within a single P-Well to achieve a high thyristor area ratio. And a carrier storage (CS) layer is introduced beneath the P⁺ region to accelerate regenerative triggering and eliminate forward snapback. These two features jointly enhance the pulse performance. Experimental results show that the SFMR-MCT delivers a peak current ( ${I}_{\text {PEAK}}\text {)}$ of 4.28 kA and a di/dt capability of 94.06 kA/ $\mu $ s at 1600 V, representing improvements of 67% and 34% over the conventional device, respectively. The device maintains stable performance under repetitive pulsed conditions, demonstrating strong potential for reliable high-voltage switching systems.

Level shifters (LSs) are essential circuit elements within high-side gate drivers, responsible for translating logic signals from a low-voltage (LV) domain to a high-voltage (HV) domain. However, high-frequency gate drivers impose stringent requirements on the propagation delay and reliability of LSs. This article presents a novel high-speed floating voltage LS that achieves subnanosecond propagation delays and enhanced noise immunity. The proposed structure, termed the common-mode self-locking (CMSL) LS, mitigates both common-mode (CM) and differential-mode (DM) noise. The proposed architecture incorporates two complementary techniques: a cross-coupled current mirror topology to suppress CM transient noise, and a combination of resistive signal sensing and a self-locking (SL) mechanism to provide DM transient noise immunity. The proposed technique achieves subnanosecond propagation delay while ensuring high noise immunity and maintaining excellent tolerance to negative voltage swings on the floating supply rail. The design is implemented in a 0.18- $\mu $ m bipolar CMOS–DMOS on the silicon-on-insulator (BCD-on-SOI) process. Simulation results demonstrate that the final LS achieves an average propagation delay as low as 410 ps. The figure of merit (FOM) is 0.057 ns/( $\mu $ m $\cdot $ V), indicating superior performance compared to existing solutions. The experimental results validate the LS’s performance, demonstrating an overall propagation delay of less than 19 ns and a dV/dt noise immunity of up to 42.8V/ns. The design supports a negative VS swing of −4.12V at a 5-V supply voltage. Furthermore, verification in a 600-V BCD process confirms the architecture’s intrinsic robustness and superior immunity performance suitable for HV applications.

A novel silicon-controlled rectifier (SCR) device is proposed to achieve adjustable holding voltage (V_h) and strong radiation tolerance. The proposed SCR devices are fabricated in 0.18-μm silicon-on-insulator (SOI) technology by inserting the very shallow trench isolation (VSTI) with different lengths in the n-well between the anode region and polysilicon. The adjustable V_h ranging from 2.0 to 4.8 V is achieved by changing the length of VSTI from 0.3 to 3 μm. The influence of total ionizing dose (TID) on VSTI-SCR devices is investigated by experiments and simulations, and strong radiation tolerance up to 500 krad(Si) is proved for the VSTI-SCRs. It is concluded that its triggering voltage decreases by about 19%–31% with the radiation dose increase from 0 to 500 krad(Si), which is beneficial for the operation of VSTI-SCR devices. V_h decreases by approximately 15%, which is overlapped by the ESD-design window of 1.2× V_DD–0.8× V_BD. Whereas, as the length of VSTI increases, V_h elevates and the effect of TID on V_h of SCR devices remains almost unchanged, which means that the latch-up risk of VSTI-SCR induced by TID could be eliminated by broadening VSTI length properly.

This paper investigates the degradation mechanism in dV/dt noise immunity robustness of traditional resistive load level shifters under total-ionizing-dose (TID) irradiation and proposes a novel radiation-hardened NMOS-R cross-coupled level shifter with dV/dt noise immunity. When TID irradiation induces threshold voltage drift and increases the OFF-state leakage current in power devices, the proposed circuit employs a differential and complementary structure to counteract the degradation of electrical performance in both branches caused by the TID irradiation, thereby achieving improved radiation-hardening performance. Measurement results demonstrate that the proposed high voltage gate drive integrated circuit (HVIC) with the novel level shifter level exhibits 130 V/ns noise immunity at the irradiation dose of 100 krad(Si). A normalization method is used to process measurement results for visual comparison. The degradation of dV/dt noise immunity capability of the proposed level shifter is improved by 26.8%, 72.4%, and 94.9% compared with the traditional level shifter at the irradiation dose of 30 krad(Si), 50 krad(Si), and 100 krad(Si). The HVIC is implemented using a 600 V silicon-on-insulator BCD process.

In digital integrated circuits with multiple power domains, level shifters (LSs) are essential circuit elements that can transform the voltage region from low to high. However, high-frequency gate drivers can generate hundreds of voltages per nanosecond noise (high dV/dt noise). Such high dV/dt noise can cause malfunction of a conventional pulse-triggered cross-coupled LS (CCLS) that is used to control the high-side nMOS switch. In this article, a novel LS with noise immunity is proposed and investigated. Compared with the conventional resistor load LS, the proposed circuit adopts nMOS-R cross-coupled (NRCC) LS, and realizes the selective filtering ability by exploiting the path that filters out the noise introduced by the dV/dt. The high-voltage gate drive integrated circuit (HVIC) is implemented using a 600 V silicon-on-insulator (SOI) BCD process. Analyses and experiments show that the proposed design can help the HVIC maintain a high common-mode transient immunity (CMTI) of up to 137 V/ns while allowing a negative VS swing down to -9.4 V under a 15 V supply voltage. Compared with the traditional HVIC with resistance load LS, the proposed novel HVIC with the NRCC LS improves the noise immunity of dV/dt by 182%.

A dual-mode buck converter with dynamic sawtooth voltage is presented in this paper. The proposed design can handle loads from 10 mA to 1000 mA by utilizing PSM and PWM modes. Moreover, there is hysteresis during mode switching from PWM to PSM to avoid the control mode fluctuating. Dynamic sawtooth voltage is used to address the line transition issue over a wide input voltage range. Implemented in 0.25 μm BCD technology, this converter can generate an output voltage of 5 V with an input voltage range of 10-55 V. The simulated results demonstrate the proper mode transition under step-up/down load current transient. The peak efficiency is 92.57% at 90 mA. The load regulation and line regulation are 1.07 μV/mA and 15.2 μV/V, respectively.