Soongyu Kang

As the number of elderly individuals living alone increases, the risk of fall-related accidents correspondingly rises, underscoring the need for rapid fall detection systems. Because falls are difficult to predict in terms of location, detection systems must be deployed in a distributed manner, which in turn requires compact and low-power implementations. Unlike camera sensors, radar sensors do not raise privacy concerns and are not limited by line-of-sight constraints. Moreover, compared with wearable sensors, radar enables continuous monitoring without user intervention. However, prior radar-based approaches incur high computational complexity, leading to increased power consumption and larger hardware area, thereby necessitating efficient hardware design. This paper proposes a lightweight fall detection system based on continuous-wave (CW) radar and a binarized convolutional neural network (BCNN). Radar signals are preprocessed using short-time Fourier transform (STFT) to generate binary spectrograms, which are then fed into a BCNN-based classification network. The proposed system performs binary classification of five fall activities and seven non-fall activities with an accuracy of 96.1%. The preprocessing module and classification network were implemented as hardware accelerators and integrated with a microprocessor in a system-on-chip (SoC) architecture on a field-programmable gate array (FPGA). Compared with the software implementation, the proposed hardware achieved speedups of 387.5× and 86.7× for the preprocessing and classification modules, respectively. Furthermore, the overall system processing time was 2.58 ms, corresponding to an 89.5× speedup over the software baseline.

In this letter, we propose a prognostics and health management (PHM) method for permanent magnet synchronous motors (PMSMs) in urban air mobility. The method uses a Transformer and three-phase current sensors. The short-time Fourier transform is employed for current signals to capture fault-related information. The Transformer architecture effectively extracts both local and global features from time–frequency representations, enabling high classification performance. However, its high computational cost and large model size hinder deployment in practical industrial applications. To address this challenge, we designed a lightweight binary-weighted Transformer (BWT) for PMSM PHM, reducing the model size to 5.5% of the baseline. The proposed BWT achieves 99.81% classification accuracy across four classes. We also developed a hardware accelerator for matrix multiplication—the most time-consuming operation in BWT—and implemented it on a field-programmable gate array. The proposed SW/HW co-design achieved an 85.55× speedup over the software-only implementation on the ARM microprocessor unit.

This paper presents a quantitative design space exploration of fast Fourier transform (FFT) architectures and numerical formats for frequency-modulated continuous-wave (FMCW) radar processing on system-on-chip (SoC) platforms. Three hardware architectures were implemented and evaluated: a memory-based single-butterfly (SB) architecture, a pipelined single-path delay-feedback (SDF) architecture, and a parallel systolic-array (SA) architecture. Two numerical formats–32-bit fixed-point (FX32) and 16-bit half-precision floating-point (FP16)–were compared in terms of latency, throughput, accuracy, and hardware efficiency. Experimental results show that the SB architecture achieves the highest resource efficiency, processing 43.72 MFrame/s per LUT and 13.68 KFrame/s per DSP in FX32, and 37.60 MFrame/s per LUT and 35.10 KFrame/s per DSP in FP16. While FP16 slightly increases LUT utilization, it significantly enhances efficiency in DSP, FF, and BRAM resources, leading to more balanced hardware utilization overall. The SA architecture delivers the shortest latency and reducing range–Doppler-map (RDM) generation time by approximately 15.61% compared with SB, albeit at the cost of over 8.9× LUT and 6.5× DSP consumption. The SDF architecture achieves moderate throughput suitable for streaming but is constrained by memory bandwidth in SoC environments. From an architectural perspective, the SB design provides the best hardware efficiency, whereas from a numerical-format perspective, FP16 offers the most favorable trade-off between precision and resource usage. At the system level, increasing the AXI data width improved processing speed by 20–26%, while burst length tuning provided smaller gains of 4–5%. The results presented in this work provide practical design guidelines for implementing efficient FFT accelerators in SoC-based FMCW radar systems.

Accidents caused by falls among the elderly have become a significant social issue, making fall detection systems increasingly needed. Fall detection systems such as internet of things (IoT) devices must be affordable and compact because they must be installed in various locations around the house, such as bedrooms, living rooms, and bathrooms. In this study, we propose a lightweight fall detection method using a continuous-wave (CW) radar sensor and a binarized neural network (BNN) to meet these requirements. We used a CW radar sensor, which is more affordable than other types of radar sensors, and employed a BNN with binarized features and parameters to reduce memory usage and make the system lighter. The proposed method distinguishes movements using micro-Doppler signatures, and spectrogram is binarized as an input to the BNN. The proposed method achieved 93.1% accuracy in binary classification of five fall actions and six non-fall actions. The memory requirements for storing parameters were reduced to 11.9 KB, representing a reduction of up to 99.9% compared with previous studies.

Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part of modern life. For low-latency AI computation in IoT systems, there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) is a machine learning algorithm well-suited for implementation on edge devices due to its simple learning and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it is easy to adjust the network structure and learn additional data. Therefore, the RCE-NN can provide edge-based real-time processing for various sensor applications. However, previous RCE-NN accelerators have limited scalability when the number of neurons increases. In this paper, we propose a network-on-chip (NoC)-based RCE-NN accelerator and present the results of implementation on a field-programmable gate array (FPGA). NoC is an effective solution for managing massive interconnections. The proposed RCE-NN accelerator utilizes a hierarchical–star (H–star) topology, which efficiently handles a large number of neurons, along with routers specifically designed for the RCE-NN. These approaches result in only a slight decrease in the maximum operating frequency as the number of neurons increases. Consequently, the maximum operating frequency of the proposed RCE-NN accelerator with 512 neurons increased by 126.1% compared to a previous RCE-NN accelerator. This enhancement was verified with two datasets for gas and sign language recognition, achieving accelerations of up to 54.8% in learning time and up to 45.7% in recognition time. The NoC scheme of the proposed RCE-NN accelerator is an appropriate solution to ensure the scalability of the neural network while providing high-performance on-chip learning and recognition.

Recently, human–machine interfaces (HMI) that make life convenient have been studied in many fields. In particular, a hand gesture recognition (HGR) system, which can be implemented as a wearable system, has the advantage that users can easily and intuitively control the device. Among the various sensors used in the HGR system, the surface electromyography (sEMG) sensor is independent of the acquisition environment, easy to wear, and requires a small amount of data. Focusing on these advantages, previous sEMG-based HGR systems used several sensors or complex deep-learning algorithms to achieve high classification accuracy. However, systems that use multiple sensors are bulky, and embedded platforms with complex deep-learning algorithms are difficult to implement. To overcome these limitations, we propose an HGR system using a binarized neural network (BNN), a lightweight convolutional neural network (CNN), with one dry-type sEMG sensor, which is implemented on a field-programmable gate array (FPGA). The proposed HGR system classifies nine dynamic gestures that can be useful in real life rather than static gestures that can be classified relatively easily. Raw sEMG data collected from a dynamic gesture are converted into a spectrogram with information in the time-frequency domain and transferred to the classifier. As a result, the proposed HGR system achieved 95.4% classification accuracy, with a computation time of 14.1 ms and a power consumption of 91.81 mW.