Lei Ge
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Research Interests
Lei Ge has a total of 174 co-authors. Here are the top co-authors by number of shared publications:
- Yujian Li
Institute of Lightwave Technology and the Key Laboratory of All Optical Network and Advanced Telecommunication Network of Ministry of Education, Beijing Jiaotong University, Beijing, China
40 shared publications - Junhong Wang
Beijing Jiaotong University
25 shared publications - Xujun Yang
Anhui Agricultural University
11 shared publications - Jianpeng Wang
Nanjing University of Science and Technology
10 shared publications - Yue Zhao
State Key Laboratory of Radio Frequency Heterogeneous Integration Shenzhen University Shenzhen China
10 shared publications - Chow-Yen-Desmond Sim
National Sun Yat-Sen University
9 shared publications
Latest Publications
- 23 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Antennas and Propagation
- Vol. 74 (4) , 3082-3095
Development of a Dual-Polarized Rectenna Enabling Asynchronous/Simultaneous Pattern-Reconfigurable Wireless Information Transfer
This article proposes a dual-polarized rectenna supporting both asynchronous and simultaneous pattern-reconfigurable wireless information transfer (WIT). The proposed rectenna design originates from the analysis of the resonant modes of a square patch. Utilizing the TM22 mode, the square patch resonator serves as four directionally-oriented baluns which share a common unbalanced port. Meanwhile, by strategically locating the feeding ports, the TM01, TM10 and TM22 modes can be excited on the patch simultaneously while maintaining excellent port isolation. The rectenna design concept was then conceived by integrating the patch resonator with four dipole structures, thus concurrently forming a radiator and a feeding network. Afterwards, three operating modes featuring dual-polarized reception for wireless power transfer (WPT) and reconfigurable patterns for WIT are developed. Specifically, mode 1 operates at 1.825 GHz for WPT, featuring a dualorthogonal polarization reception. For mode 2, it supports asynchronous WIT at 5.04 GHz with quad-directional pattern reconfigurability. Building on modes 1 and 2, mode 3 enables simultaneous wireless information and power transfer (SWIPT), supporting dual-directional WIT pattern reconfiguration concurrently with WPT. Furthermore, by introducing a self-powered reconfiguration scheme to mode 3, the WIT pattern can indirectly be reconfigured by switching the WPT transmitting polarization. To support this scheme, a high-output-power voltage doubler rectifier is designed, achieving a peak RF-to-DC conversion efficiency of 78%. Ultimately, experiments are conducted to verify the feasibility of the proposed rectenna.
- 23 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Antennas and Propagation
- Vol. 74 (4) , 3082-3095
Development of a Dual-Polarized Rectenna Enabling Asynchronous/Simultaneous Pattern-Reconfigurable Wireless Information Transfer
This article proposes a dual-polarized rectenna supporting both asynchronous and simultaneous pattern-reconfigurable wireless information transfer (WIT). The proposed rectenna design originates from the analysis of the resonant modes of a square patch. Utilizing the TM22 mode, the square patch resonator serves as four directionally-oriented baluns which share a common unbalanced port. Meanwhile, by strategically locating the feeding ports, the TM01, TM10 and TM22 modes can be excited on the patch simultaneously while maintaining excellent port isolation. The rectenna design concept was then conceived by integrating the patch resonator with four dipole structures, thus concurrently forming a radiator and a feeding network. Afterwards, three operating modes featuring dual-polarized reception for wireless power transfer (WPT) and reconfigurable patterns for WIT are developed. Specifically, mode 1 operates at 1.825 GHz for WPT, featuring a dualorthogonal polarization reception. For mode 2, it supports asynchronous WIT at 5.04 GHz with quad-directional pattern reconfigurability. Building on modes 1 and 2, mode 3 enables simultaneous wireless information and power transfer (SWIPT), supporting dual-directional WIT pattern reconfiguration concurrently with WPT. Furthermore, by introducing a self-powered reconfiguration scheme to mode 3, the WIT pattern can indirectly be reconfigured by switching the WPT transmitting polarization. To support this scheme, a high-output-power voltage doubler rectifier is designed, achieving a peak RF-to-DC conversion efficiency of 78%. Ultimately, experiments are conducted to verify the feasibility of the proposed rectenna.
- 16 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Antennas and Propagation
- Vol. 74 (4) , 2999-3009
Horizontally and Circularly Polarized Omnidirectional Filtering Dielectric Resonator Antenna
This paper presents a horizontally polarized (HP) omnidirectional filtering dielectric resonator (DR) antenna (DRA) and its circularly polarized (CP) counterpart, without extra filtering circuits. The HP filtering DRA comprises a DR and a single-layer circular substrate. A modified end-shorted Alford loop with center-shorted parasitic strips is positioned on the top of the substrate, two concentric circular slots are etched on the bottom. Wherein, the inner slot consists of four open stubs. This configuration excites three operating modes: the TE011+δ DR mode and two patch modes. Through mode cancellation between these modes, two radiation nulls are created near the passband, thus realizing filtering responses. The CP filtering design shares a highly similar structure with the HP one. The key difference lies in its bottom side, which features a single circular slot integrated with both open and shorted stubs. This setup enables filtering responses with left hand circular polarization (LHCP). Both the HP and CP filtering designs were fabricated and measured. The HP DRA features a measured -10-dB impedance bandwidth of 19% and a realized gain of 1.25 dBi within the passband. It has an electrical size of π×0.252×0.19λ03. The CP design has an overlapped -10-dB impedance and 3-dB axial ratio (AR) bandwidth of 11.9%, with a realized gain of 0.7 dBic. Whereas, its electrical size increases to π×0.282×0.18λ03. Both designs show omnidirectional radiation patterns with suppression levels over 19 dB and 13.3 dB, respectively.
- 16 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Antennas and Propagation
- Vol. 74 (4) , 2999-3009
Horizontally and Circularly Polarized Omnidirectional Filtering Dielectric Resonator Antenna
This paper presents a horizontally polarized (HP) omnidirectional filtering dielectric resonator (DR) antenna (DRA) and its circularly polarized (CP) counterpart, without extra filtering circuits. The HP filtering DRA comprises a DR and a single-layer circular substrate. A modified end-shorted Alford loop with center-shorted parasitic strips is positioned on the top of the substrate, two concentric circular slots are etched on the bottom. Wherein, the inner slot consists of four open stubs. This configuration excites three operating modes: the TE011+δ DR mode and two patch modes. Through mode cancellation between these modes, two radiation nulls are created near the passband, thus realizing filtering responses. The CP filtering design shares a highly similar structure with the HP one. The key difference lies in its bottom side, which features a single circular slot integrated with both open and shorted stubs. This setup enables filtering responses with left hand circular polarization (LHCP). Both the HP and CP filtering designs were fabricated and measured. The HP DRA features a measured -10-dB impedance bandwidth of 19% and a realized gain of 1.25 dBi within the passband. It has an electrical size of π×0.252×0.19λ03. The CP design has an overlapped -10-dB impedance and 3-dB axial ratio (AR) bandwidth of 11.9%, with a realized gain of 0.7 dBic. Whereas, its electrical size increases to π×0.282×0.18λ03. Both designs show omnidirectional radiation patterns with suppression levels over 19 dB and 13.3 dB, respectively.
- Open Access
- 1 January 2026
- Published by Institution of Engineering and Technology (IET) in IET Microwaves, Antennas & Propagation
- Vol. 20 (1) , e70091
360° Beam‐Steering Substrate‐Integrated Waveguide Horn Antenna Loaded Monopole Array for Millimetre‐Wave Communications
A millimetre-wave tilting beam-steering substrate-integrated waveguide (SIW) horn antenna is proposed for millimetre-wave communications. First, a six-port reconfigurable SIW feeding network using PIN diodes is designed for beam-steering and each output terminal is directly connected to a horn antenna. Second, to address problems of impedance matching and narrow bandwidth, the horn antenna aperture is loaded with extra substrates and a dipole array. Furthermore, a loaded U-shaped wall improves the antenna gain and front-to-back ratio (FTBR) by suppressing backward radiation. Finally, to enhance the compactness of the previous SIW antenna and generate tilting beams, a tilting beam-steering SIW horn antenna is proposed and fabricated to tilt the beam in the direction. This antenna incorporates a monopole array and a metal reflector ground. The measured results indicate an impedance bandwidth with dB from 25.60 to 27.72 GHz, a peak gain of 10.5 dBi, and an FTBR exceeding 15 dB. The proposed antenna, which covers a beam-steering range of in the azimuth plane and up to in the elevation plane, offers a simple and compact structure, high FTBR and full directional coverage without blind spots.- 1 January 2026
- Published by Institution of Engineering and Technology (IET) in IET Microwaves, Antennas & Propagation
- Vol. 20 (1) , e70091
Open Access360° Beam‐Steering Substrate‐Integrated Waveguide Horn Antenna Loaded Monopole Array for Millimetre‐Wave Communications
A millimetre-wave tilting beam-steering substrate-integrated waveguide (SIW) horn antenna is proposed for millimetre-wave communications. First, a six-port reconfigurable SIW feeding network using PIN diodes is designed for beam-steering and each output terminal is directly connected to a horn antenna. Second, to address problems of impedance matching and narrow bandwidth, the horn antenna aperture is loaded with extra substrates and a dipole array. Furthermore, a loaded U-shaped wall improves the antenna gain and front-to-back ratio (FTBR) by suppressing backward radiation. Finally, to enhance the compactness of the previous SIW antenna and generate tilting beams, a tilting beam-steering SIW horn antenna is proposed and fabricated to tilt the beam in the direction. This antenna incorporates a monopole array and a metal reflector ground. The measured results indicate an impedance bandwidth with dB from 25.60 to 27.72 GHz, a peak gain of 10.5 dBi, and an FTBR exceeding 15 dB. The proposed antenna, which covers a beam-steering range of in the azimuth plane and up to in the elevation plane, offers a simple and compact structure, high FTBR and full directional coverage without blind spots. - 19 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 34 (2) , 568-578
A 95.3% 12-Class, 108-nJ/Inference Keyword Spotting Chip With Hybrid FFT-BFNet Architecture and Exponent-Aware Nonuniform Quantization in 65-nm CMOS
This article presents a 65-nm keyword spotting (KWS) chip that achieves 95.3% accuracy on 12-class tasks with 108.04-nJ/inference efficiency through cross-domain hardware-algorithm innovations. The unified fast Fourier transform (FFT)-butterfly-structured neural network (BFNet) accelerator fundamentally rethinks computational reuse: by replacing dense pointwise convolutions with butterfly-based sparse operations mirroring FFT’s dataflow, it slashes$6.3\times $ multiply-accumulate (MAC) operations and halves parameter counts while preserving model expressivity. A 6-bit exponent-aware nonuniform quantization (EANUQ) scheme compresses weights, achieving a 25% reduction in storage while maintaining an accuracy loss of less than 0.01% with lightweight on-chip decoders. Hardware resource sharing extends beyond computation: Mel-filter-banks reuse fully-connected (FC) layer multipliers through decomposed 8-bit arithmetic, and FFT output buffers double as convolutional neural network (CNN) feature map memory. Measured at 0.65 V/600 kHz, the 0.58-$\text {mm}^{2}$ core demonstrates$1.9\times $ –$15.5\times $ better energy efficiency than prior 65/28-nm implementations, with 14.82-ms end-to-end latency.- 19 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 34 (2) , 568-578
A 95.3% 12-Class, 108-nJ/Inference Keyword Spotting Chip With Hybrid FFT-BFNet Architecture and Exponent-Aware Nonuniform Quantization in 65-nm CMOS
This article presents a 65-nm keyword spotting (KWS) chip that achieves 95.3% accuracy on 12-class tasks with 108.04-nJ/inference efficiency through cross-domain hardware-algorithm innovations. The unified fast Fourier transform (FFT)-butterfly-structured neural network (BFNet) accelerator fundamentally rethinks computational reuse: by replacing dense pointwise convolutions with butterfly-based sparse operations mirroring FFT’s dataflow, it slashes$6.3\times $ multiply-accumulate (MAC) operations and halves parameter counts while preserving model expressivity. A 6-bit exponent-aware nonuniform quantization (EANUQ) scheme compresses weights, achieving a 25% reduction in storage while maintaining an accuracy loss of less than 0.01% with lightweight on-chip decoders. Hardware resource sharing extends beyond computation: Mel-filter-banks reuse fully-connected (FC) layer multipliers through decomposed 8-bit arithmetic, and FFT output buffers double as convolutional neural network (CNN) feature map memory. Measured at 0.65 V/600 kHz, the 0.58-$\text {mm}^{2}$ core demonstrates$1.9\times $ –$15.5\times $ better energy efficiency than prior 65/28-nm implementations, with 14.82-ms end-to-end latency.