Andrea Lico

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to its high density, scalability, and analog non-volatile storage capability. This article presents a PCM-based (Ge-rich GST) analog IMC (AIMC) macro designed for multilayer, drift- and temperature-resilient computation. Fabricated in a 28-nm FD-SOI CMOS process and integrating a 4M-cell array, the accelerator achieves a matrix–vector multiplication (MVM) error lower than 2.14% across a wide temperature range (from $-\textbf {40}~^{\circ }\textbf {C}$ to $+125~^{\circ }\textbf {C}$ ), yielding a $\textbf {3.5}\times $ improvement over state-of-the-art solutions according to an FoM defined as No. of Weights $\times $ TOPS/W/mm², a metric that reflects the achievable storage-energy efficiency per area during computation.

This article presents a high-precision close-to-analog programming methodology for phase-change memory (PCM) cells, targeting analog in-memory computing (AiMC) architectures for edge-artificial intelligence (AI) applications. By leveraging an iterative accumulation approach during the verify phase, the proposed technique enhances the effective number of bits (ENOBs) achievable in PCM cells. Experimental validation on a 28-nm STMicroelectronics FD-SOI PCM-based AiMC macro demonstrates the capability to accurately program large-scale matrix-vector multiplication (MVM) weights. The results highlight the potential of the proposed programming scheme to overcome intrinsic device variability, resulting in high accuracy in MVM computation. The methodology also shows promising applicability for mapping deep neural network (DNN) and large language model (LLM) weights with high precision, reaching an ENOB of 10.5.

This brief presents a design technique to linearize the frequency-to-conductance characteristic of a Current-Controlled Oscillator (CCO) within a CCO-based ADC used for Matrix-Vector Multiplication (MVM) in Analog in-Memory Computing (AiMC) accelerators. The proposed linearization is achieved by leveraging a bitline voltage regulator (BLVR), a circuit commonly employed to bias the bitlines (BLs) of computational resistive memory arrays. The BLVR utilizes a resistor and a copy of the bitline current to create a feedback mechanism that dynamically adjusts the bitline voltage in response to changes in the total bitline conductance ( $\boldsymbol {g_{BL}}$ ). This feedback reduces the oscillation period by an amount that linearizes the relationship between the CCO output frequency ( $\boldsymbol {f_{CCO}}$ ) and $\boldsymbol {g_{BL}}$ . Simulations in 28 nm FD-SOI technology demonstrate that the proposed BLVR reduces the quadratic coefficient $\boldsymbol {k_{2}}$ of a polynomial approximation of the $\boldsymbol {f_{CCO}}$ – $\boldsymbol {g_{BL}}$ characteristic from $\boldsymbol {5.88\times 10^{-2}}$ to $\boldsymbol {2.31\times 10^{-2}}$ , corresponding to a $\boldsymbol {2.5\times }$ improvement in linearity in the full conductance range.

Phase Change Memory (PCM) has emerged as a promising non-volatile memory technology with significant applications in both edge computing and analog in-memory computing. This paper synthesizes recent research contributions on the use of PCM for smart sensing, structural health monitoring, neural network acceleration, and binary pattern matching. By examining key advancements, challenges, and potential future developments, this work provides a comprehensive state-of-the-art overview of PCM in these domains, highlighting the possible employments of PCM technology in further edge computing scenarios including medical and human body monitoring.

This article introduces a method to mitigate conductance time drift of phase-change memory (PCM) cells for improved resilience of matrix-vector multiplication (MVM) in analog in-memory computing (AIMC) systems. The proposed approach consists of on-chip current-induced annealing of each PCM device to stabilize its conductance at a target level, avoiding any rearrangement of the cell lattice. The procedure is performed within the programming phase of PCM devices with no severe constraints on execution time because of the infrequent update of MVM weights in deep neural networks (DNNs). Experimental validations were conducted on a 90-nm STMicroelectronics CMOS Ge-rich GeSbTe (GST)-embedded PCM targeting 16 conductance levels, and results indicate that the average time drift and variability of cells conductance are reduced by at least a factor of 2.3 and 3.5, respectively, compared with standard programming. Simulations based on empirical results reveal a 0.8% MVM accuracy loss after 12 h at room temperature and 4.8% after an additional 64-h bake at 85 $^{\circ}$ C, with a considerable increase in MVM computing retention compared with those granted with standard programming. Accuracy loss is minimized to around 1% even at high temperatures when the proposed method is combined with hardware drift compensation.

This paper presents a readout scheme for Analog In-memory Computing (AIMC) based on an embedded Phase-change Memory (ePCM). Conductance time drift is overcome with a hardware compensation technique based on a reference cell conductance tracking (RCCT). Accuracy drop due to circuits mismatch and variability involved in the computational chain are minimized with an optimized iterative program-and-verify algorithm applied to the PCM devices. The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed Multiply-and-Accumulate (MAC) computation feature to a Ge-rich GeSbTe (GST) embedded PCM array. Experimental characterizations are performed under different operating conditions, and show that mean MAC decrease in time is approximately null at room temperature and reduced by a factor of 3 after 64-hours bake at 85∘C. Based on several MAC operations, the estimated 512×512 Matrix-Vector-Multiplication (MVM) accuracy is 97.4%, whose decrease in time is less than 3% in the worst case.

Analog In-Memory computing (AIMC) is a novel paradigm looking for solutions to prevent the unnecessary transfer of data by distributing computation within memory elements. One such operation is matrix-vector multiplication (MVM), a workhorse of many fields ranging from linear regression to Deep Learning. The same concept can be readily applied to the encoding stage in Compressed Sensing (CS) systems, where an MVM operation maps input signals into compressed measurements. With a focus on an encoder built on top of a Phase-Change Memory (PCM) AIMC platform, the effects of device non-idealities, namely programming spread and drift over time, are observed in terms of the reconstruction quality obtained for synthetic signals, sparse in the Discrete Cosine Transform (DCT) domain. PCM devices are simulated using statistical models summarizing the properties experimentally observed in an AIMC prototype, designed in a 90 nm STMicroelectronics technology. Different families of decoders are tested, and tradeoffs in terms of encoding energy are analyzed. Furthermore, the benefits of a hardware drift compensation strategy are also observed, highlighting its necessity to prevent the need for a complete reprogramming of the entire analog array. The results show >30 dB average reconstruction quality for mid-range conductances and a suitably selected decoder right after programming. Additionally, the hardware drift compensation strategy enables robust performance even when different drift conditions are tested.