Yarden Siton

The paper presents a methodology for determining the minimum split DC link capacitance for a family of three-phase, three-level grid-connected bidirectional AC-DC converters operating under arbitrary power factor under restriction of DC-only zero-sequence injection. The approach is based on the recently revealed generalized behavior of split DC link voltages in the above-mentioned converters family while distinguishing between leading and lagging power factors in order to highlight different impacts on split DC link capacitor voltages pulsating components. The minimum capacitance value is derived from the boundary condition, ensuring the mains voltage remains below or equal to the capacitor voltage at all times. It is revealed that operation with the lowest expected leading power factor should be employed as the design operating point. The accuracy of the proposed methodology is validated by simulations and experiments carried out employing a 10 kVA grid-connected T-type converter prototype. The results demonstrate close agreement between theoretical predictions and experiments, confirming the practical applicability of the proposed method.

This article examines the impact of a power factor on the behavior of partial DC link voltages in three-phase three-level AC/DC (or DC/AC) converters operating without additional balancing hardware. We consider the case in which the controller utilizes a bandwidth-restricted (DC in steady state) zero-sequence component to achieve average partial DC link voltage equalization since the injection of high-order zero-sequence components is impossible or forbidden. An assessment of partial split DC-link capacitor voltage behavior (particularly that of ripple magnitudes and phases) is necessary for, e.g., minimizing the values of DC link capacitances and selecting reference voltage values. Previous studies assessed the abovementioned behavior analytically for operation under a unity power factor based on third-harmonic-dominated split partial voltages’ ripple nature. However, it is shown here that deviation from the unity power factor introduces additional (to the third harmonic) non-negligible harmonic content, increasing partial voltage ripple magnitudes and shifting their phase (relative to the mains voltages). As a result, the third-harmonic-only assumption is no longer valid, and it is then nearly impossible to derive corresponding analytical expressions. Consequently, a numerical approach is used in this work to derive a generalized expression of normalized ripple energy as a function of the power factor, which can then easily be utilized for assessments of split DC link voltage behaviors for certain DC link capacitances and reference voltages. Simulations and experimental results validate the proposed methodology applied to a 10 kVA T-type converter prototype.

This paper introduces an approach to calculating the minimum value of split DC link capacitance in three-phase three-level grid-connected DC-AC converters operating with unity power factor without either active balancing circuits or AC zero sequence injection. Due to the fact that partial DC link voltages and rectified mains phase voltages reach their maximum and minimum values, respectively, at different time instants, it is feasible to decrease the minimum value of the former below the maximum value of the latter while still maintaining proper functionality of the power stage. The minimum possible split DC link capacitance values are hence derived from the boundary condition where the above-mentioned voltages are tangent to each other. The accuracy of the analytical derivations is confirmed by simulations and experiments carried out on a 10 kVA T-type converter prototype, which show a high degree of agreement.