Kirill A. Buzaverov

Silicon nitride (SiN) is currently the most prominent platform for photonics in the visible and near-IR wavelength bandwidth. However, realizing fast electro-optic modulators, the key components of any integrated optics platform remain challenging in SiN. Recently, transparent conductive oxides have emerged as a promising platform for photonic integrated circuits. In this work, we take an important step toward combining the advantages of both platforms, reporting for the high-speed indium tin oxide electro-optic modulators based on silicon nitride waveguides. We demonstrate a bandwidth higher than 1 GHz, 9.3-μm-length active element, and an insertion loss of 5.7 dB for a 300 nm-thickness SiN waveguide platform. Simulation results of optimized device designs indicate that further improvements are possible, offering promising opportunities for silicon nitride photonic integrated circuit platform combined with indium oxide-based layers.

Photonic integrated circuits play a crucial role in almost every aspect of modern life, such as data storage, telecommunications, medical diagnostics, green energy, autonomous driving, agriculture, and high-performance computing. To fully harness their benefits, an efficient coupling mechanism is required to successfully launch light into on-chip waveguides from fibers. This study introduces low-loss coupling strategies and their implementation for silicon nitride integrated photonics. Here we present an overview of coupling technologies, optimized designs, and a fabrication technique for inverse tapers, which enable effective coupling for both transverse-magnetic and transverse-electric modes. We measured the coupling losses of 0.15 dB for UHNA-7 fiber at 1550 nm per facet for single-mode 220 × 1200 nm waveguides. We also designed, fabricated, and experimentally characterized a multi-tip taper, yielding 1.5 dB per facet at 1550 nm with broadband stability over 1500–1600 nm. We believe that our approach is universal and can be used both for individual fiber and fiber arrays coupling and for subsequent assembly of fiber with a chip, ensuring minimal losses.

Silicon nitride (Si₃N₄) photonic integrated circuits (PICs) are of great interest due to their extremely low propagation loss and higher integration capabilities. The number of applications based on the silicon nitride integrated photonics platform continues to grow, including the Internet of Things (IoT), artificial intelligence (AI), light detection and ranging (LiDAR), hybrid neuromorphic and quantum computing. It's potential for CMOS compatibility, as well as advances in heterogeneous integration with silicon‐on‐insulator, indium phosphate, and lithium niobate on insulator platforms, are leading to an advanced hybrid large‐scale PICs. Here, they review key trends in Si₃N₄ photonic integrated circuit technology and fill an information gap in the field of state‐of‐the‐art devices operating from the visible to the mid‐infrared spectrum. A comprehensive overview of its microfabrication process details (deposition, lithography, etching, etc.) is introduced. Finally, the limitations and challenges of silicon nitride photonics performance are pointed out in an ultra‐wideband, providing routes and prospects for its future scaling and optimization.

Low-loss photonic integrated circuits (PICs) are the key elements in future quantum technologies, nonlinear photonics and neural networks. The low-loss photonic circuits technology targeting C-band application is well established across multi-project wafer (MPW) fabs, whereas near-infrared (NIR) PICs suitable for the state-of-the-art single-photon sources are still underdeveloped. Here, we report the labs-scale process optimization and optical characterization of low-loss tunable photonic integrated circuits for single-photon applications. We demonstrate the lowest propagation losses to the date (as low as 0.55 dB/cm at 925 nm wavelength) in single-mode silicon nitride submicron waveguides (220×550 nm). This performance is achieved due to advanced e-beam lithography and inductively coupled plasma reactive ion etching steps which yields waveguides vertical sidewalls with down to 0.85 nm sidewall roughness. These results provide a chip-scale low-loss PIC platform that could be even further improved with high quality SiO₂ cladding, chemical-mechanical polishing and multistep annealing for extra-strict single-photon applications.

High-quality factor plasmonic devices are crucial components in the fields of nanophotonics, quantum computing and sensing. The majority of these devices are required to be fabricated on non-lattice matched or transparent amorphous substrates. Plasmonic devices quality factor is mainly defined by ohmic losses, scattering losses at grain boundaries, and in-plane plasmonic scattering losses of a metal – substrate system. Here, we demonstrate the deposition technique to e-beam evaporate ultralow-loss silver thin films on transparent lattice-mismatched substrates. The process is based on evolutionary selection growth. The key feature of our approach is a well-defined control of deposition on a cooled substrate, self-crystallization and subsequent annealing for precise stress relaxation that promote further grains growth. We are able to deposit 100-nm thick ultraflat polycrystalline silver films with micrometer-scale grains and ultralow optical losses. Finally, we show ultra-high-quality factor plasmonic silver nanostructures on transparent lattice-mismatched substrate comparable to epitaxial silver. This can be of the great interest for high performance or single-molecule optical sensorics applications.

Advanced microsystems widely used in integrated optoelectronic devices, energy harvesting components, and microfluidic lab-on-chips require high-aspect silicon microstructures with a precisely controlled profile. Such microstructures can be fabricated using the Bosch process, which is a key process for the mass production of micro-electro-mechanical systems (MEMS) devices. One can measure the etching profile at a cross-section to characterize the Bosch process quality by cleaving the substrate into two pieces. However, the cleaving process of several neighboring deeply etched microstructures is a very challenging and uncontrollable task. The cleaving method affects both the cleaving efficiency and the metrology quality of the resulting etched microstructures. The standard cleaving technique using a diamond scriber does not solve this issue. Herein, we suggest a highly controllable cross-section cleaving method, which minimizes the effect on the resulting deep etching profile. We experimentally compare two cleaving methods based on various auxiliary microstructures: (1) etched transverse auxiliary lines of various widths (from 5 to 100 μm) and positions; and (2) etched dashed auxiliary lines. The interplay between the auxiliary lines and the etching process is analyzed for dense periodic and isolated trenches sized from 2 to 50 μm with an aspect ratio of more than 10. We experimentally showed that an incorrect choice of auxiliary line parameters leads to silicon “build-up” defects at target microstructures intersections, which significantly affects the cross-section profile metrology. Finally, we suggest a highly controllable defect-free cross-section cleaving method utilizing dashed auxiliary lines with the stress concentrators.