Guangyu Zhang

Two-dimensional semiconductors, featuring atomic-scale thickness, excellent electrostatic gate control, and outstanding electrical properties, hold great promise for next-generation electronics. Recently, monolayer MoS2, a typical two-dimensional semiconductor, has been extensively explored for field-effect transistors (FETs). However, its atomically thin channel is highly sensitive to environmental exposure and interfacial perturbations, leading to significant performance degradation. Here, we report a low-temperature (200 °C), intrinsic sulfur passivation strategy to form a nondestructive capping layer on monolayer MoS2 FETs. This capping layer effectively isolates the channel from ambient species while passivating sulfur vacancy defects. As a result, the electrical performance is markedly improved, leading to a positive threshold voltage shift of 1.5 V and a substantial reduction in hysteresis from 2 V to 160 mV. Notably, the devices exhibit excellent environmental stability, maintaining their performance after 180 days under ambient conditions. Based on this approach, rail-to-rail inverters are realized using a pristine MoS2 load transistor and an S-capped MoS2 driver transistor, achieving a high voltage gain of 175.11 with symmetric noise margins (noise margin high ≈ 1.82 V and noise margin low ≈ 1.82 V). Importantly, large-scale inverter arrays demonstrate excellent device uniformity and reproducibility in performance. Furthermore, the scalability of this strategy is demonstrated via various fundamental logic circuits, including NOR and NAND gates, as well as a five-stage ring oscillator. These results highlight the effectiveness of sulfur passivation in enabling high-performance, stable, and scalable MoS2-based electronic and integrated circuit applications.

Ferroelectric flux-closures are promising candidates for high-performance memories, offering reversible switching and low power consumption. However, integration of ferroelectric flux-closures into memory devices is elusive, mostly due to the constraint from the substrate on which polar film is grown. Here, we demonstrate ferroelectric field-effect transistors (Fe-FETs) based on freestanding films with identical polar flux-closures. The retention of flux-closure in the freestanding film is driven by the intrinsic self-organization of polarization to minimize the combined elastic and electrostatic energies. The flux-closure structures exhibit low coercive electric field (E_c), negligible leakage currents, and endurance up to 10¹⁰ cycles. Furthermore, the as-fabricated complementary metal-oxide-semiconductor (CMOS)-compatible Fe-FET arrays achieve reversible information writing and erasure. They set a benchmark for perovskite-structured devices by simultaneously achieving a large memory window of 0.43 V/nm and a high on/off ratio of 10⁸, while maintaining endurance and stability. Our work paves the way for ferroelectric devices in future semiconductor industries.

Regarding thin film growth, it has been widely recognized that the film typically follows the surface texture and high sharp steps potentially lead to growth termination and film discontinuity. Here, we demonstrate an abnormality that monolayer MoS ₂ grown on C -plane sapphire is able to cross sharp steps up to ∼10 nm in height. Assisted by theoretical simulations, we unveil that the cross-step growth of monolayer MoS ₂ results from the competition between its deformation energy cost and adsorption energy gain. Notably, cross-step growth leads to the formation of one-dimensional (1D) ripples on target substrates after transfer, resulting in symmetry breaking and strain engineering to trigger anisotropic properties and boost transistor performances. The room-temperature mobility (on-state current) along the ripple direction is improved by ∼67.6% (∼118.4%) compared to that perpendicular to the ripple direction. Our work showcases an exotic cross-step growth paradigm to create and manipulate 2D materials, promising the prospect for a broad portfolio of emerging electronic, photonic, and optoelectronic applications.

Alternating twisted multilayer graphene presents a compelling multiband system, with a coexistence of Dirac bands and flat bands, for exploring superconductivity. However, the roles of flat bands and Dirac bands played in determining the superconductivity remain elusive. Here, we focus on the alternating twisted quadralayer graphene to reveal unconventional superconducting behaviors. We disentangle Dirac bands and flat bands, revealing a Coulomb interaction-induced band broadening effect. We further quantify the electric-field-dependent evolution of the critical temperature and coherence length, and estimate the flat-band Fermi velocity and superfluid stiffness via critical current measurements. Our results demonstrate an electric-field-tunable coupling strength within the superconducting phase, revealing unconventional properties with vanishing Fermi velocity and large superfluid stiffness. Combined with our theoretical analysis, these observations support a picture in which displacement-field-driven hybridization between flat and Dirac-like bands enhances the quantum-metric contribution to superconductivity, offering new insight into multiband flat-band superconductivity in moiré systems.

Moiré superlattice based on rhombohedral graphene is an emerging strongly correlated platform for exploring novel quantum states and phase transitions. Here, we report the observation of symmetry-breaking states and phase transitions in a newly discovered twisted rhombohedral trilayer-bilayer graphene (tRTBG) moiré superlattice. At zero magnetic fields, we observe displacement field-driven resistance jumps and hysteresis loops across the symmetry-breaking phase boundaries, providing evidence for first-order phase transitions. The observation of hysteresis loops driven by out-of-plane and in-plane magnetic fields at the boundaries reveals the lifted spin degeneracy in symmetry-breaking metals and correlated insulators. We further investigate the evolution of symmetry-breaking phases and their phase boundaries under finite magnetic fields, revealing rich competition between states with different symmetries. Our findings uncover the isospin-polarized orders in correlated states and enrich the phase diagram of tRTBG, providing new insights into interaction-driven phases in twisted rhombohedral graphene.

Hardware-level security is crucial for establishing trust in the rapidly expanding Internet-of-Things (IoT) and edge computing systems. A promising approach employs physical unclonable functions (PUFs) which leverage intrinsic process variations to generate unique and irreproducible identifiers. However, conventional silicon-based PUFs often suffer from limited entropy and lack of reconfigurability, becoming vulnerable to machine learning attacks. Here, we present an optically reconfigurable PUF based on a 64-cell array of five-stage ring oscillators fabricated from wafer-scale monolayer MoS₂. The system exhibits spectrally selective frequency shifts under red, green, and blue (RGB) illumination, establishing a dynamic optical entropy dimension that enables on-demand, reversible rekeying without hardware modification. We develop a robust key-generation pipeline combining within-chip normalization, random-projection q-ary quantization, and the Secure Hash Algorithm 256 (SHA-256) privacy amplification, followed by hash-based message authentication code (HMAC)-based key derivation. The resulting keys demonstrate near-ideal uniformity (~50%) and inter-device Hamming distance (~0.677 at q = 3, 39 ~ 0.761 at q = 4), while remaining resilient to advanced machine learning attacks (≤ 52% accuracy). We further demonstrate image encryption and authentication with noise-like ciphertexts and reliable tamper detection. This work introduces a promising class of material-intrinsic, optically addressable security primitives for trusted edge computing applications.

Interlayer insertion has emerged as one of the key strategies for contact engineering in two-dimensional (2D) field-effect transistors (FETs). However, conventional interlayers such as hexagonal boron nitride (hBN) offers limitations in contacts performance and face challenges in achieving low-thermal-budget large-area fabrication. In this work, we explore the functionalization of printed ultrathin gallium oxide (GaOx) films as tunneling contact layer in 2D transistors. Leveraging self-limiting oxidation of liquid gallium, we fabricate nanometer-thick GaOx films (3.6 nm) that possess shallow defect states arising from oxygen vacancies, thereby narrowing the tunneling barrier width. When integrated as a tunneling layer in multilayer WS2 field-effect transistors, the GaOx film significantly enhances device performance, achieving a record electron mobility of 296 cm2 V-1 s-1, ultra-low contact resistance of 2.38 kΩ·μm, and a minimal contact barrier height of 3.7 meV. Distinct from conventional insulating tunneling dielectrics, the observed performance enhancement originates from a hybrid tunneling mechanism within GaOx, activated under the synergy of multiple electric fields and temperature. Oxygen vacancies act as dynamic conduction channels that mediate composite tunneling pathways combining defect-assisted, direct, and Fowler–Nordheim tunneling, thus enabling efficient carrier injection across the interface. In addition, the low-temperature printing method also enables van der Waals integration in scalable fabrication without Fermi pinning effect. This study not only demonstrates the new functional application of printed GaOx films and clarifies the role of its oxygen vacancies in tunneling mechanism, but also proposes a novel, scalable strategy for optimizing contact engineering in low-dimensional electronic devices.

The discovery of novel ferroelectric compounds and the modulation of polarization in established ferroelectric materials have persistently represented crucial and highly dynamic areas of research within the field of ferroelectric materials science. Here we demonstrate a structural templating strategy to reconfigure Aurivillius-phase oxides into metastable ferroelectric phases with tailored polarization. By stabilizing a metastable WO₃ phase within a Bi₂WO₆ framework, we achieve robust out-of-plane polarization (10 µC/cm²) in textured WO₃/Bi₂WO₆ films, contrasting the purely in-plane polarization of pristine Bi₂WO₆. First-principles calculations and atomic-resolution scanning transmission electron microscopy unveil a WO₃ phase with oxygen displacement-driven ferroelectricity. Prototype ferroelectric field-effect transistors and memristors fabricated from these films exhibit robust switching ratios (>10⁶) and thermal stability up to 350 °C. This work not only expands the family of binary ferroelectric oxides but also establishes a generalizable paradigm for overcoming polarization-directionality constraints in layered ferroelectrics.

Artificial Intelligence (AI), has been occupying the central position in recent technological advancement, propelled by exponentially increasing computing resources, which in turn stimulate the demand on higher level 3D integration for integrated circuits. However, current frontside-only integration is inevitably bottlenecked by the routing congestion and parasitic degradation on the wafer frontside, blocking the further down scaling. Fortunately, the underutilized backside space of wafer provides inimitable opportunities to break this blockage. Here, we demonstrate the "Flip 3D" (F3D) technology which utilizes both sides of wafer to capture the ultra-high-density connectivity of monolithic integration while maintaining the architectural flexibility of heterogeneous integration. F3D technology enables the co-integration of logic, memory, and connectivity with significantly reduced interconnect parasitics. Experimentally, F3D technology was verified on a FinFET test vehicle in a dual-sided form, successfully integrating logic, temperature sensors, optical modules, on-chip memory, and high-density computing-in-memory cells. We further introduce "Hyper 3D" (H3D) technology for dual-sided system-on-wafer integration. Our results validate that this unified dual-sided scheme provides effective solution to the "computing," "memory," and "connectivity" walls. This work establishes a scalable roadmap for multi-layer on-chip systems, providing a full-3D hardware strategy for the next generation of AI hardware.